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Hardware support for inter-process communication and processor sharing

Authors:

W. S. Ford,

V. C. HamacherAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 4, Issue 4

Pages 113 - 118

https://doi.org/10.1145/633617.803559

Published: 17 January 1976 Publication History

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Abstract

The abstraction of a computer system as a set of asynchronous communicating processes is an important system concept. This paper indicates how the concept could be supported at a low hardware level. A new inter-process communication mechanism called a mailbox is introduced. Examples of its use as a programming tool are given. This is followed by a description of hardware features that use this mechanism as the basis of communication between the components of a complete system. These features include processor-sharing hardware capable of handling process selection and switching with high efficiency. It is also indicated how these features can take the place of conventional input/output structures.

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Cited By

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Zertal STimsit CChatti M(2009)Communication/synchronisation mechanism for multiprocessor on Chip architectures2009 IEEE Symposium on Computers and Communications10.1109/ISCC.2009.5202412(62-66)Online publication date: Jul-2009
https://doi.org/10.1109/ISCC.2009.5202412
Preiss BHamacher VSiegel H(1988)A cache-based message passing scheme for a shared-bus multiprocessorProceedings of the 15th Annual International Symposium on Computer architecture10.5555/52400.52440(358-364)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/52400.52440
Preiss BHamacher V(1988)A cache-based message passing scheme for a shared-bus multiprocessorACM SIGARCH Computer Architecture News10.1145/633625.5244016:2(358-364)Online publication date: 17-May-1988
https://dl.acm.org/doi/10.1145/633625.52440
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Index Terms

Hardware support for inter-process communication and processor sharing
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
2. Social and professional topics
  1. Professional topics
    1. Management of computing and information systems
      1. Implementation management
        Pricing and resource allocation
      2. Information system economics

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 4, Issue 4

January 1976

210 pages

ISSN:0163-5964

DOI:10.1145/633617

Issue’s Table of Contents

ISCA '76: Proceedings of the 3rd annual symposium on Computer architecture
January 1976
215 pages
ISBN:9781450374132
DOI:10.1145/800110
Chairmen:
Michael J. Flynn,
Oscar N. Garcia,
Daniel P. Siewiorek

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 January 1976

Published in SIGARCH Volume 4, Issue 4

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Cited By

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Zertal STimsit CChatti M(2009)Communication/synchronisation mechanism for multiprocessor on Chip architectures2009 IEEE Symposium on Computers and Communications10.1109/ISCC.2009.5202412(62-66)Online publication date: Jul-2009
https://doi.org/10.1109/ISCC.2009.5202412
Preiss BHamacher VSiegel H(1988)A cache-based message passing scheme for a shared-bus multiprocessorProceedings of the 15th Annual International Symposium on Computer architecture10.5555/52400.52440(358-364)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/52400.52440
Preiss BHamacher V(1988)A cache-based message passing scheme for a shared-bus multiprocessorACM SIGARCH Computer Architecture News10.1145/633625.5244016:2(358-364)Online publication date: 17-May-1988
https://dl.acm.org/doi/10.1145/633625.52440
Reghbati HHamacher VMcCluskey EWakerly JCrockett EBredt TLu DvanCleemput WOwicki SOgus RApte RBeaurdy MLosq J(1978)Hardware support for concurrent programming in loosely coupled multiprocessorsProceedings of the 5th annual symposium on Computer architecture10.1145/800094.803048(195-201)Online publication date: 3-Apr-1978
https://dl.acm.org/doi/10.1145/800094.803048

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Abstract

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