Article

On achieving balanced power consumption in software pipelined loops

Authors:

Clement LeungAuthors Info & Claims

CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 210 - 217

https://doi.org/10.1145/581630.581663

Published: 08 October 2002 Publication History

Abstract

While a significant body of work in compilers has been devoted to reducing energy consumption in embedded systems, the role of a compiler in harnessing the power variation has not been widely explored. Since sharp power variations across time steps cause power supply noises and degrade reliability of functional blocks, power variation is a design constraint in embedded systems. With the advent of high performance embedded systems and extensive deployment of fine grain clock-gating, reducing variations in power is becoming increasingly important.This paper studies how compilation techniques, more specifically instruction scheduling, can ameliorate variations in power due to functional units during program execution. By extending our previous work on rate-optimal software pipelining, this paper formulates the problem of constructing a performance-optimal schedule that minimizes power variations as an integer linear programming (ILP) problem. The formulation can be solved using an ILP solver. We applied our approach on <tt>SPEC NAS</tt> benchmarks to construct software pipelined schedules that have minimum power variations. The benchmarks are executed on the Wattch power simulator. In comparison to the original (power-unaware) scheduler implemented in the MIPSpro compiler, our power-aware approach generates schedules which have significantly lower power variations while maintaining the same performance. Such schedules have the potential to reduce hardware cost on power delivery in designing embedded systems.

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Cited By

Kabrick RPerdomo DRaskar SDiaz JFox DGao G(2020)CODIR: Towards an MLIR Codelet Model Dialect2020 IEEE/ACM Fourth Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM)10.1109/IPDRM51949.2020.00009(33-40)Online publication date: Nov-2020
https://doi.org/10.1109/IPDRM51949.2020.00009
Lin CHuang CKuan CHuang SLee J(2015)The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/269983420:2(1-27)Online publication date: 2-Mar-2015
https://dl.acm.org/doi/10.1145/2699834
Lin CKuan CShih WLee J(2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1007/s11265-014-0917-9
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Index Terms

On achieving balanced power consumption in software pipelined loops
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Published In

cover image ACM Conferences

CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

October 2002

324 pages

ISBN:1581135750

DOI:10.1145/581630

General Chairs:
Shuvra S. Bhattacharyya
University of Maryland
,
Trevor Mudge
University of Michigan
,
Program Chairs:
Wayne Wolf
Princeton University
,
Ahmed Jerraya
TIMA, Grenoble, France

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 October 2002

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Cited By

Kabrick RPerdomo DRaskar SDiaz JFox DGao G(2020)CODIR: Towards an MLIR Codelet Model Dialect2020 IEEE/ACM Fourth Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM)10.1109/IPDRM51949.2020.00009(33-40)Online publication date: Nov-2020
https://doi.org/10.1109/IPDRM51949.2020.00009
Lin CHuang CKuan CHuang SLee J(2015)The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/269983420:2(1-27)Online publication date: 2-Mar-2015
https://dl.acm.org/doi/10.1145/2699834
Lin CKuan CShih WLee J(2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1007/s11265-014-0917-9
Chen CChang R(2015)Thermal-aware code transformation across functional unitsConcurrency and Computation: Practice & Experience10.1002/cpe.325327:3(594-609)Online publication date: 10-Mar-2015
https://dl.acm.org/doi/10.1002/cpe.3253
Lin CKuan CLee J(2013)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsProceedings of the 2013 42nd International Conference on Parallel Processing10.1109/ICPP.2013.125(1052-1060)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1109/ICPP.2013.125
Rahman SGuo JBhat AGarcia CSujon MYi QLiao CQuinlan DFeo JFaraboschi PVilla O(2012)Studying the impact of application-level optimizations on the power consumption of multi-core architecturesProceedings of the 9th conference on Computing Frontiers10.1145/2212908.2212927(123-132)Online publication date: 15-May-2012
https://dl.acm.org/doi/10.1145/2212908.2212927
Rahman SGuo JYi QKatevenis MMartonosi MKozyrakis CTemam O(2011)Automated empirical tuning of scientific codes for performance and power consumptionProceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers10.1145/1944862.1944880(107-116)Online publication date: 24-Jan-2011
https://dl.acm.org/doi/10.1145/1944862.1944880
Chen CChang R(2011)Thermal-Aware Code Transformation across Functional UnitsProceedings of the 2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2011.70(300-305)Online publication date: 24-Oct-2011
https://dl.acm.org/doi/10.1109/EUC.2011.70
Lin CChen PTseng CHuang CWeng CKuan CLin SHuang SLee JGivargis TDonlin A(2010)Power aware SID-based simulator for embedded multicore DSP subsystemsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1878981(95-104)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878961.1878981
Bahuleyan JNagpal RSrikant Y(2010)Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)10.1109/IPDPSW.2010.5470906(1-8)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPSW.2010.5470906
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