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Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors

Published: 02 October 2002 Publication History

Abstract

This article describes a new approach to HW-SW codesign for complex embedded systems, using high-level programming languages. Unlike in previous approaches, the designer does not need to acquire new skills, because most of the design process is automated. The hardware extensions are implemented as simple coprocessors consisting of a reconfigurable datapath and a control memory. Our approach is demonstrated with a simple image processing application, obtaining a 100% performance improvement.

References

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S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. Piperench: a coprocessor for streaming multimedia acceleration. ISCA, 1999.
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S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The Chimaera reconfigurable functional unit. IEEE Symposium on FPGAs for Custom Computing Machines, pages 87--96, 1997.
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R. Hauser and J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 1997.
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Yanbing Li, Tim Callahan, Ervan Darnell, Randolf Harr, Uday Kurkure, and Jon Stockwood. Hardware-Software Co-Design of Embedded Reconfigurable Architectures. In Design Automation Conference, 2000.
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Cited By

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  • (2010)ReferencesSystem Level Design with .Net Technology10.1201/9781439812129.bmatt(281-296)Online publication date: 19-Feb-2010
  • (2007)Efficient FPGA hardware developmentJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.09.01053:4(184-209)Online publication date: 1-Apr-2007
  • (2006)Automatic Generation of Embedded Systems with .NET Framework Based Tools2006 IEEE North-East Workshop on Circuits and Systems10.1109/NEWCAS.2006.250904(165-168)Online publication date: Nov-2006

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Published In

cover image ACM Conferences
ISSS '02: Proceedings of the 15th international symposium on System Synthesis
October 2002
278 pages
ISBN:1581135769
DOI:10.1145/581199
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 02 October 2002

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Author Tags

  1. hardware-software codesign
  2. reconfigurable datapaths

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ISSS '02 Paper Acceptance Rate 38 of 71 submissions, 54%;
Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

View all
  • (2010)ReferencesSystem Level Design with .Net Technology10.1201/9781439812129.bmatt(281-296)Online publication date: 19-Feb-2010
  • (2007)Efficient FPGA hardware developmentJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.09.01053:4(184-209)Online publication date: 1-Apr-2007
  • (2006)Automatic Generation of Embedded Systems with .NET Framework Based Tools2006 IEEE North-East Workshop on Circuits and Systems10.1109/NEWCAS.2006.250904(165-168)Online publication date: Nov-2006

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