Test structures for delay variability

With continued technology scaling, yield loss due to timing variation is becoming a significant concern. In particular, random and systematic process variation in devices and interconnect results in variable delay and operating speed along different logic and signal paths; these variations can erode timing windows and ultimately contribute to circuit failure. In this work, a test structure methodology is developed to support the evaluation of process variation and its impact on circuit speed.A newly designed variation test chip enables relatively simple measurement and evaluation of timing variation resulting from process and layout-induced variation. First, the fundamental test structure is a nine-stage ring oscillator (RO); a frequency-divided readout of the RO frequency serves as a clearly defined measure of circuit speed. A large family of ring oscillator test structures has been designed, where each structure is made sensitive to a particular device or interconnect variation source. Front-end-of-line (FEOL) or device variation sensitive structures enable examination of channel length variation as a function of different layout practices, including gate length (finger width), spacing between multiple fingers, orientation (vertical or horizontal), and density of poly fill. Back-end-of-line (BEOL) or interconnect sensitive structures enable examination of variation in dielectric or metal thickness at different metal levels and impact on interconnect capacitance.The second key element of the test structure methodology is a scan-chain architecture enabling independent operation and readout of replicated ring oscillator test structures. In this second version test chip, designed and fabricated in $0.25 m technology, over 2000 ring oscillators per chip can be measured using simple digital control and readout circuitry interfaced to the packaged chip. The scan chain approach involves reading in a control word to each ring oscillator, which specifies if that oscillator is to operate and if the RO frequency is to be put onto an output bus into frequency division and output circuitry. Additional test chip design elements include separate ring oscillator and control logic power grids, so that the frequency dependence of the ring oscillators on power supply voltage can also be measured, enabling separation of channel length and threshold voltage variation contributions.A $0.25 µm version of the test chip has been fabricated, and measurement and statistical analysis of 35 chips have been successfully conducted. Results indicate that within-wafer variation continues to be larger than within-chip variation; however, systematic spatial patterns and layout-dependent variations within the chip are substantial and of particular concern in timing (which depends on matched signal delays across a chip or logic block). The test chip can be ported to other advanced technologies to provide information on layout-dependent and spatially-dependent process variation sources of timing variation, to aid in statistical timing analysis as well as help specify layout practices and design rules to minimize variation.