Article

Power-aware modulo scheduling for high-performance VLIW processors

Authors:

Han-Saem Yun,

Jihong KimAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 40 - 45

https://doi.org/10.1145/383082.383091

Published: 06 August 2001 Publication History

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Cited By

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Zhong HLiu Z(2023)Long-life Sensitive Modulo Scheduling with Adaptive Loop Expansion2022 IEEE 28th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS56603.2022.00075(530-537)Online publication date: Jan-2023
https://doi.org/10.1109/ICPADS56603.2022.00075
Zhong HLiu ZLiu SMa SLi C(2022)Adaptive Low-Cost Loop Expansion for Modulo SchedulingNetwork and Parallel Computing10.1007/978-3-031-21395-3_3(30-41)Online publication date: 1-Dec-2022
https://doi.org/10.1007/978-3-031-21395-3_3
Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Show More Cited By

Index Terms

Power-aware modulo scheduling for high-performance VLIW processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
  2. Electronic design automation
    1. Modeling and parameter extraction

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Zhong HLiu Z(2023)Long-life Sensitive Modulo Scheduling with Adaptive Loop Expansion2022 IEEE 28th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS56603.2022.00075(530-537)Online publication date: Jan-2023
https://doi.org/10.1109/ICPADS56603.2022.00075
Zhong HLiu ZLiu SMa SLi C(2022)Adaptive Low-Cost Loop Expansion for Modulo SchedulingNetwork and Parallel Computing10.1007/978-3-031-21395-3_3(30-41)Online publication date: 1-Dec-2022
https://doi.org/10.1007/978-3-031-21395-3_3
Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Ahmed FSabry MAtienza DMilor L(2012)Wearout-aware compiler-directed register assignment for embedded systemsThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187471(33-40)Online publication date: Mar-2012
https://doi.org/10.1109/ISQED.2012.6187471
Reddi VPan DNassif SBowman K(2012)Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6165064(7-16)Online publication date: Jan-2012
https://doi.org/10.1109/ASPDAC.2012.6165064
Nagpal RSrikant Y(2011)Compiler-assisted power optimization for clustered VLIW architecturesParallel Computing10.1016/j.parco.2010.08.00537:1(42-59)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1016/j.parco.2010.08.005
Guan YXue J(2011)Leakage-Aware Modulo Scheduling for Embedded VLIW ProcessorsJournal of Computer Science and Technology10.1007/s11390-011-1143-626:3(405-417)Online publication date: 12-May-2011
https://doi.org/10.1007/s11390-011-1143-6
Reddi VCampanoni SGupta MSmith MWei GBrooks DHazelwood K(2010)Eliminating voltage emergencies via software-guided code transformationsACM Transactions on Architecture and Code Optimization10.1145/1839667.18396747:2(1-28)Online publication date: 5-Oct-2010
https://dl.acm.org/doi/10.1145/1839667.1839674
Sabry MAyala JAtienza DBahar RLombardi FAtienza DBrunvand E(2010)Thermal-aware compilation for system-on-chip processing architecturesProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785535(221-226)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785535
Sabry MAyala JAtienza D(2010)Thermal-Aware Compilation for Register Window-Based Embedded ProcessorsIEEE Embedded Systems Letters10.1109/LES.2010.20813432:4(103-106)Online publication date: 1-Dec-2010
https://dl.acm.org/doi/10.1109/LES.2010.2081343
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