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Register Allocation for Banked Register File

Published: 01 August 2001 Publication History

Abstract

A banked register file is a register file partitioned into banks. A register in a banked register file is addressed with the register number in conjunction with the active bank number. A banked register file may be employed to reduce the number of bits for register operands in the instruction encoding at the cost of bank changes and inter-bank data transfers. Although a banked register file is introduced to provide sufficient registers and reduce memory traffic, it may on the other hand inflate code by unwanted bank hanges and excessive inter-bank data movements. In this context, code quality heavily depends on the register allocator that decides the location of each variable. This paper addresses a heuristic approach to register allocation for exploiting two register banks. It performs global register allocation with the primary bank registers, while reducing the register pressure by doing local register allocation with the secondary bank registers. Experimental results show that the proposed register allocator eliminates a significant amount of memory traffic while achieving smaller code size compared to an allocator that utilizes the primary bank only.

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  • (2021)Improving performance and determinism of multitasking systems on the LEON architectureMicroprocessors & Microsystems10.1016/j.micpro.2020.10361080:COnline publication date: 1-Feb-2021
  • (2010)Register file partitioning and recompilation for register file power reductionACM Transactions on Design Automation of Electronic Systems10.1145/1754405.175440915:3(1-30)Online publication date: 10-Jun-2010
  • (2009)Advances in Register Allocation TechniquesThe Compiler Design Handbook10.1201/9781420043839.ch21(21-1-21-27)Online publication date: 7-Dec-2009
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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 36, Issue 8
    Aug. 2001
    245 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/384196
    Issue’s Table of Contents
    • cover image ACM Conferences
      LCTES '01: Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems
      August 2001
      250 pages
      ISBN:1581134258
      DOI:10.1145/384197
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 August 2001
    Published in SIGPLAN Volume 36, Issue 8

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    Author Tags

    1. banked register file
    2. register allocation

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    • (2021)Improving performance and determinism of multitasking systems on the LEON architectureMicroprocessors & Microsystems10.1016/j.micpro.2020.10361080:COnline publication date: 1-Feb-2021
    • (2010)Register file partitioning and recompilation for register file power reductionACM Transactions on Design Automation of Electronic Systems10.1145/1754405.175440915:3(1-30)Online publication date: 10-Jun-2010
    • (2009)Advances in Register Allocation TechniquesThe Compiler Design Handbook10.1201/9781420043839.ch21(21-1-21-27)Online publication date: 7-Dec-2009
    • (2008)Reducing power consumption of embedded processors through register file partitioning and compiler supportProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580190(269-274)Online publication date: 2-Jul-2008
    • (2007)Carbon nanotubes as counter electrode for dye-sensitised solar cellsElectronics Letters10.1049/el:2007286743:25(1455)Online publication date: 2007
    • (2005)A register allocation framework for banked register files with access constraintsProceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11572961_22(269-280)Online publication date: 24-Oct-2005
    • (2019)Compiling with code-size constraintsACM SIGPLAN Notices10.1145/566225.51385137:7(120-129)Online publication date: 5-Jun-2019
    • (2018)Balanced bipartite graph based register allocation for network processors in mobile and wireless networksMobile Information Systems10.1155/2010/9861926:1(65-83)Online publication date: 16-Dec-2018
    • (2017)Region-based dual bank register allocation for reduced instruction encoding ArchitecturesMicroprocessors & Microsystems10.1016/j.micpro.2017.09.00555:C(26-43)Online publication date: 1-Nov-2017
    • (2009)Comparison of Bank Change Mechanisms for Banked Reduced Encoding ArchitecturesProceedings of the 2009 International Conference on Computational Science and Engineering - Volume 0210.1109/CSE.2009.358(334-341)Online publication date: 29-Aug-2009
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