Gigue: A JIT Code Binary Generator for Hardware Testing
Pages 73 - 82
Abstract
Just-in-time compilers are the main virtual machine components responsible for performance. They recompile frequently used source code to machine code directly, avoiding the slower interpretation path. Hardware acceleration and performant security primitives would benefit the generated JIT code directly and increase the adoption of hardware-enforced primitives in a high-level execution component.
The RISC-V instruction set architecture presents extension capabilities to design and integrate custom instructions. It is available as open-source and several capable open-source cores coexist, usable for prototyping. Testing JIT-compiler-specific instruction extensions would require extending the JIT compiler itself, other VM components, the underlying operating system, and the hardware implementation. As the cost of hardware prototyping is already high, a lightweight representation of the JIT compiler code region in memory would ease prototyping and implementation of new solutions.
In this work, we present Gigue, a binary generator that outputs bare-metal executable code, representing a JIT code region snapshot composed of randomly filled methods. Its main goal is to speed up hardware extension prototyping by defining JIT-centered workloads over the newly defined instructions. It is modular and heavily configurable to qualify different JIT code regions' implementations from VMs and different running applications. We show how the generated binaries can be extended with three custom extensions, whose execution is guaranteed by Gigue's testing framework. We also present different application case generation and execution on top of a fully-featured RISC-V core.
References
[1]
CHIPS Alliance. 2023. Chisel/FIRRTL Hardware Compiler Framework. https://www.chisel-lang.org/
[2]
Krste Asanovic, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, and Adam Izraelevitz. 2016. The Rocket chip generator.
[3]
Fabrice Bellard. 2005. QEMU, a Fast and Portable Dynamic Translator. In Proceedings of the USENIX Annual Conference (ATEC’05). 41–46. https://www.usenix.org/legacy/events/usenix05/tech/freenix/bellard.html
[4]
Asmit De, Aditya Basu, Swaroop Ghosh, and Trent Jaeger. 2019. FIXER: Flow integrity extensions for embedded RISC-V. In Proceedings of the 26th Design, Automation & Test in Europe Conference & Exhibition (DATE’19). 348–353. https://doi.org/10.23919/date.2019.8714980
[5]
Quentin Ducasse. 2023. Gigue: Benchmark Setup and Code Generator for JIT code on RISC-V. https://github.com/qducasse/gigue
[6]
Quentin Ducasse, Guillermo Polito, Pablo Tesone, Pascal Cotret, and Loïc Lagadec. 2022. Porting a JIT Compiler to RISC-V: Challenges and Opportunities. In Proceedings of the 19th International Conference on Managed Programming Languages and Runtimes (MPLR’22). 112–118. https://doi.org/10.1145/3546918.3546924
[7]
Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, and Luca Benini. 2020. PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors. Philosophical Transactions of the Royal Society A (RSTA), 378 (2020), https://doi.org/10.1098/rsta.2019.0155
[8]
Urs Hölzle, Craig Chambers, and David Ungar. 1991. Optimizing dynamically-typed object-oriented languages with polymorphic inline caches. In Proceedings of the 6th ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (ECOOP’91). 21–38. https://doi.org/10.1007/bfb0057013
[9]
Dan Ingalls, Ted Kaehler, John Maloney, Scott Wallace, and Alan Kay. 1997. Back to the Future: The Story of Squeak, a Practical Smalltalk Written in Itself. In Proceedings of the 12th ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA’97). 318–326. https://doi.org/10.1145/263698.263754
[10]
Haeyoung Kim, Jinjae Lee, Derry Pratama, Asep Muhamad Awaludin, Howon Kim, and Donghyun Kwon. 2020. RIMI: instruction-level memory isolation for embedded systems on RISC-V. In Proceedings of the 39th International Conference on Computer-Aided Design (ICCAD’20). 1–9. https://doi.org/10.1145/3400302.3415727
[11]
Arjun Menon, Subadra Murugan, Chester Rebeiro, Neel Gala, and Kamakoti Veezhinathan. 2017. Shakti-T: a RISC-V processor with light weight security extensions. In Proceedings of the 6th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP’17). 1–8. https://doi.org/10.1145/3092627.3092629
[12]
Eliot Miranda. 2011. The Cog Smalltalk virtual machine. In Proceedings of the 5th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages (VMIL’11).
[13]
Guillermo Polito, Pablo Tesone, Stéphane Ducasse, Luc Fabresse, Théo Rogliano, Pierre Misse-Chanabier, and Carolina Hernandez Phillips. 2021. Cross-ISA testing of the Pharo VM: lessons learned while porting to ARMv8. In Proceedings of the 18th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes (MPLR’21). 16–25. https://doi.org/10.1145/3475738.3480715
[14]
Nguyen Anh Quynh. 2014. Capstone: Next-gen disassembly framework. https://www.capstone-engine.org/BHUSA2014-capstone.pdf Black Hat USA
[15]
Nguyen Anh Quynh and Dang Hoang Vu. 2015. Unicorn: Next generation CPU emulator framework. https://www.unicorn-engine.org/BHUSA2015-unicorn.pdf Black Hat USA
[16]
riscv-software src. 2023. riscv-tests. https://github.com/riscv-software-src/riscv-tests
[17]
Moritz Schneider, Ramya Jayaram Masti, Shweta Shinde, Srdjan Capkun, and Ronald Perez. 2022. SoK: hardware-supported trusted execution environments. Computing Research Repository (CoRR), https://doi.org/10.48550/arXiv.2205.12742
[18]
Veripool. 2023. Verilator. https://www.veripool.org/verilator/
[19]
Andrew Waterman, Krste Asanovic, and SiFive Inc. 2019. The RISC-V instruction set manual, Volume I: unprivileged ISA. https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
[20]
Andrew Waterman, Krste Asanovic, and SiFive Inc. 2021. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12
Index Terms
- Gigue: A JIT Code Binary Generator for Hardware Testing
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Published: 19 October 2023
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