GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking
Pages 123 - 126
Abstract
Logic locking is a technique for the protection of hardware intellectual property (IP) from malicious entities like piracy, overproduction, reverse engineering, etc. The register transfer level (RTL) locking performs the locking on RTL description for protection of the IP even from the early design cycle. TAO [12] is such a locking scheme that employs locking during the high-level synthesis (HLS) process. In this paper, we evaluate the unlocking capability of the genetic algorithm (GA) by performing attacks on the RTLs locked using TAO based technique. We demonstrate the ability of GA to unlock TAO generated RTLs in seconds. Our GA based attack is faster as compared to the Satisfiability Modulo Theories (SMT) based attack [9]. The GA based method also converges well in most of the cases as shown in the experimental results.
Supplementary Material
This presentation focuses on the challenges faced in the domain of hardware security. Register Transfer Level(RTL) locking is a locking mechanism to aid security and safety in the RTL design of a circuit. An attack on the RTL locked circuit using Genetic algorithm(GA) has been demonstrated to check the robustness of the RTL locking. The GA is found to be effective as it unlocks most of the test cases.
- Download
- 188.49 MB
References
[1]
Abderehman, M., Patidar, J., Oza, J., Nigam, Y., Khader, T. A., and Karfa, C. Fastsim: A fast simulation framework for high-level synthesis. IEEE TCAD (2021), 1--1.
[2]
Badier, H., Lann, J.-C. L., Coussy, P., and Gogniat, G. Transient key-based obfuscation for hls in an untrusted cloud environment. In DATE (2019), pp. 1118--1123.
[3]
Baumgarten, A., Tyagi, A., and Zambreno, J. Preventing ic piracy using reconfigurable logic barriers. IEEE D&T of Computers 27, 1 (2010), 66--75.
[4]
Chakraborty, P., Cruz, J., Alaql, A., and Bhunia, S. Sail: Analyzing structural artifacts of logic locking using machine learning. IEEE TIFS 16 (2021), 3828--3842.
[5]
Chen, H., Fu, C., Zhao, J., and Koushanfar, F. Genunlock: An automated genetic algorithm framework for unlocking logic encryption. In ICCAD (2019), pp. 1--8.
[6]
Han, Z., Yasin, M., and Rajendran, J. J. Does logic locking work with EDA tools? In 30th USENIX Security Symposium (USENIX Security 21) (2021).
[7]
John, M., Hoda, A., Chouksey, R., and Karfa, C. Sat based partial attack on compound logic locking. In 2020 AsianHOST (2020), pp. 1--6.
[8]
Karfa, C., Chouksey, R., Pilato, C., Garg, S., and Karri, R. Is register transfer level locking secure? In DATE (2020), pp. 550--555.
[9]
Kasarabada, Y., Chen, S., and Vemuri, R. On sat-based attacks on encrypted sequential logic circuits. In ISQED (2019), pp. 204--211.
[10]
Pilato, C., Chowdhury, A. B., Sciuto, D., Garg, S., and Karri, R. Assure: Rtl locking against an untrusted foundry. IEEE TVLSI 29, 7 (2021), 1306--1318.
[11]
Pilato, C., Regazzoni, F., Karri, R., and Garg, S. Tao: Techniques for algorithm-level obfuscation during high-level synthesis. In DAC (2018), pp. 1--6.
[12]
Rajendran, J., Ali, A., Sinanoglu, O., and Karri, R. Belling the cad: Toward security-centric electronic system design. IEEE TCAD 34, 11 (2015), 1756--1769.
[13]
Sirone, D., and Subramanyan, P. Functional analysis attacks on logic locking. In DATE (2019), pp. 936--939.
[14]
Subramanyan, P., Ray, S., and Malik, S. Evaluating the security of logic encryption algorithms. In 2015 IEEE HOST (2015), pp. 137--143.
[15]
Xie, Y., and Srivastava, A. Anti-sat: Mitigating sat attack on logic locking. IEEE TCAD (2018), 199--207.
[16]
Yasin, M., Mazumdar, B., Rajendran, J., and Sinanoglu, O. Sarlock: Sat attack resistant logic locking. In HOST (2016), pp. 236--241.
[17]
Yasin, M., Sengupta, A., Nabeel, M., Ashraf, M., Rajendran, J., and Sinanoglu, O. Provably-secure logic locking: From theory to practice. In ACM SIGSAC CCS (2017), pp. 1601--1618.
Index Terms
- GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking
Recommendations
Is register transfer level locking secure?
DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in EuropeRegister Transfer Level (RTL) locking seeks to prevent intellectual property (IP) theft of a design by locking the RTL description that functions correctly on the application of a key. This paper evaluates the security of a state-of-the-art RTL locking ...
Designing ML-resilient locking at register-transfer level
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferenceVarious logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no ...
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
ISVLSI '08: Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSIThis paper presents a methodology for design space exploration (DSE) in high-level synthesis (HLS), based on a multi-objective genetic algorithm. Since all high-level synthesis sub-tasks are notoriously NP-complete and interdependent and the design ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
June 2022
560 pages
ISBN:9781450393225
DOI:10.1145/3526241
- General Chairs:
- Ioannis Savidis,
- Avesta Sasan,
- Program Chairs:
- Himanshu Thapliyal,
- Ronald F. DeMara
Copyright © 2022 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 06 June 2022
Check for updates
Author Tags
Qualifiers
- Short-paper
Conference
GLSVLSI '22
Sponsor:
Acceptance Rates
Overall Acceptance Rate 312 of 1,156 submissions, 27%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 82Total Downloads
- Downloads (Last 12 months)5
- Downloads (Last 6 weeks)0
Reflects downloads up to 19 Nov 2024
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in