research-article

Efficient and scalable core multiplexing with M³v

Authors:

Sebastian Haas,

Carsten Weinhold,

Michael RoitzschAuthors Info & Claims

ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

Pages 452 - 466

https://doi.org/10.1145/3503222.3507741

Published: 22 February 2022 Publication History

Abstract

The M³ system (ASPLOS ’16) proposed a hardware/software co-design that simplifies integration between general-purpose cores and special-purpose accelerators, allowing users to easily utilize them in a unified manner. M³ is a tiled architecture, whose tiles (cores and accelerators) are partitioned between applications, such that each tile is dedicated to its own application. The M³x system (ATC ’19) extended M³ by trading off some isolation to enable coarse-grained multiplexing of tiles among multiple applications. With M³x, if source tile t₁ runs code of application p and sends a message m to destination tile t₂ while t₂ is currently not associated with p, then m is forwarded to the right place through a “slow path”, via some special OS tile. In this paper, we present M³v, which extends M³x by further trading off some isolation between applications to support “fast path” communication that does not require the said OS tile’s involvement. Thus, with M³v, a tile can be efficiently multiplexed between applications provided it is a general-purpose core. M³v achieves this goal by 1) adding a local multiplexer to each such core, and by 2) virtualizing the core’s hardware component responsible for cross-tile communications. We prototype M³v using RISC-V cores on an FPGA platform and show that it significantly outperforms M³x and may achieve competitive performance to Linux.

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ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

February 2022

1164 pages

ISBN:9781450392051

DOI:10.1145/3503222

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Suresh VMishra BJing YZhu ZJin NBlock CMantovani PGiri DZuckerman JCarloni LAdve S(2024)Mozart: Taming Taxes and Composing Accelerators with Shared-MemoryProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676896(183-200)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676896
Asmussen NHaas SLackorzyński ARoitzsch M(2024) Core-Local Reasoning and Predictable Cross-Core Communication with M 3 2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00024(199-211)Online publication date: 13-May-2024
https://doi.org/10.1109/RTAS61025.2024.00024
Haas SDunkel CPauls FHasler MVerma Y(2024)Trustworthy Silicon: An MPSoC for a Secure Operating System2024 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS64408.2024.10752473(1-7)Online publication date: 29-Oct-2024
https://doi.org/10.1109/NorCAS64408.2024.10752473
Weinhold CAsmussen NGöhringer DRoitzsch M(2023)Towards Modular Trusted Execution EnvironmentsProceedings of the 6th Workshop on System Software for Trusted Execution10.1145/3578359.3593037(10-16)Online publication date: 8-May-2023
https://dl.acm.org/doi/10.1145/3578359.3593037
Haas SAsmussen N(2022)A Trusted Communication Unit for Secure Tiled Hardware Architectures2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9971056(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9971056
Haas SHasler MPauls FKopsell SAsmussen NRoitzsch MFettweis G(2022)Trustworthy Computing for O-RAN: Security in a Latency-Sensitive Environment2022 IEEE Globecom Workshops (GC Wkshps)10.1109/GCWkshps56602.2022.10008543(826-831)Online publication date: 4-Dec-2022
https://doi.org/10.1109/GCWkshps56602.2022.10008543

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