research-article

IMAC:: A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit

Authors:

Bindu G. Gowda,

Madhav RaoAuthors Info & Claims

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

Pages 503 - 508

https://doi.org/10.1145/3583781.3590265

Published: 05 June 2023 Publication History

Abstract

Multiply-and-accumulate (MAC) units are primarily utilized for convolution operations targeted towards signal and image processing workload. The compressors are applied at the partial product reduction stages to extract the multiplier output bits, which are later accumulated with an extra adder unit. The paper proposes an integrated approach where the other operand of the MAC unit is directly fed to the partial-product-matrix (PPM) before the product bits are evaluated. This integrated Multiplier-and-Accumulate (IMAC) approach saves an additional adder unit and instead extends the compressor, which is already used to reduce partial-product bits of the multiplier design. Compressors employed exact and approximate IMAC architectures were designed and evaluated through ASIC and FPGA flow. Five versions of inexact IMAC design were independently compared with traditional one-level approximation and two-level approximation in MAC designs. The proposed work is found to be hardware efficient when compared with state-of-art MAC units. The error metrics were either comparable or better for IMAC design when compared with separately designed approximate multipliers followed by exact or approximate adder units. The image blending application was considered to measure the quality metrics. The proposed IMAC design files are made freely available for further usage by the research and development community.

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Cited By

Devi DAjay Kumar GG Gowda BRao M(2024)Integrated MAC-based Systolic Arrays: Design and Performance EvaluationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658797(292-295)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658797
Devi DKumar GGowda BRao M(2024)Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528695(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528695
Gowda BN RC PNandi PRao M(2023)ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00017(46-53)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00017

Index Terms

IMAC:: A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
      2. Combinational circuits
    2. Reconfigurable logic and FPGAs
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific integrated circuits

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Published In

cover image ACM Conferences

GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023

June 2023

731 pages

ISBN:9798400701252

DOI:10.1145/3583781

General Chairs:
Himanshu Thapliyal
University of Tennessee, Knoxville, USA
,
Ronald DeMara
University of Central Florida, USA
,
Program Chairs:
Inna Partin-Vaisband
University of Illinois Chicago, USA
,
Srinivas Katkoori
University of South Florida, USA

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 05 June 2023

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GLSVLSI '23: Great Lakes Symposium on VLSI 2023

June 5 - 7, 2023

TN, Knoxville, USA

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Cited By

Devi DAjay Kumar GG Gowda BRao M(2024)Integrated MAC-based Systolic Arrays: Design and Performance EvaluationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658797(292-295)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658797
Devi DKumar GGowda BRao M(2024)Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528695(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528695
Gowda BN RC PNandi PRao M(2023)ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00017(46-53)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00017

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