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A new partitioning method for parallel simulation of VLSI circuits on transistor level

Authors:

Norbert Fröhlich,

Volker Glöckel,

Josef FleischmannAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 679 - 685

https://doi.org/10.1145/343647.343892

Published: 01 January 2000 Publication History

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Lyras GRodopoulos DPapanikolaou ASoudris DMacii E(2013)Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485448(655-658)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485448

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A new partitioning method for parallel simulation of VLSI circuits on transistor level
1. Hardware

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For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors ...
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For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors ...
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The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among ...

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Published In

DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

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Published: 01 January 2000

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Lyras GRodopoulos DPapanikolaou ASoudris DMacii E(2013)Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485448(655-658)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485448

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A new approach for partitioning VLSI circuits on transistor level

A new approach for partitioning VLSI circuits on transistor level

Designing new ternary reversible subtractor circuits