Contributions to openroad from abroad: experiences and learnings
Authors: 
Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo ReisAuthors Info & Claims
Article No.: 113, Pages 1 - 8
Abstract
The OpenROAD project is an ambitious initiative seeking to develop an automated, open-source RTL-to-GDSII flow. To build its complex toolset, OpenROAD brings together a team of industry experts, veteran scholars, and enthusiastic students from different schools and different countries. This paper first presents our path to becoming OpenROAD contributors, highlighting the nature of the OpenROAD project, the recruitment process, and the necessary logistics. We then summarize the contributions of the Brazilian team to the OpenROAD project; these comprise the development of five tools and more than 10K lines of released code, along with authorship or co-authorship of two publications in the research literature. We also summarize our experiences from working in a large software project: (i) working environment and relationship with people from around the world; (ii) task management and short turnaround times; (iii) continuous integration and testing; etc. Finally, we highlight the challenges of "refurbishing" academic research codes for use in the design of production ICs.
References
[1]
C. J. Alpert, W.-K. Chow, K. Han, A. B. Kahng, Z. Li, D. Liu and S. Venkatesh, "Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees", Proc. ISPD, 2018, pp. 10--17.
[2]
C. Chu and Y.-C. Wong, "FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design", IEEE TCAD, 27 (2008), pp. 70--83.
[3]
M. Fogaça, A. B. Kahng, E. Monteiro, R. Reis, L. Wang and M. Woo, "On the Superiority of Modularity-Based Clustering for Determining Placement-Relevant Clusters", Integration: The VLSI Journal 74 (2020), pp. 32--44.
[4]
V. Bandeira, M. Fogaça, E. Monteiro, I. Oliveira, M. Woo and R. Reis, "Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching", Proc. NEWCAS, 2020, pp. 1--4.
[5]
K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", IEEE TCAD, 2020, pp. 478--491.
[6]
M. Guiney and E. Leavitt, "An Introduction to Openaccess an Open Source Data Model and API for IC Design", Proc. ASPDAC, 2006, pp. 434--436.
[7]
S. Mantik, G. Posser, W.-K. Chow, Y. Ding, and W.-H. Liu, "ISPD 2018 Initial Detailed Routing Contest and Benchmarks", Proc. ISPD, 2018, pp. 140--143.
[8]
M. Pan and C. Chu, "FastRoute: A Step to Integrate Global Routing into Placement", Proc. ICCAD, 2006, pp. 464--471.
[9]
M. Pan and C. Chu, "FastRoute 2.0: A High-quality and Efficient Global Router", Proc. ASPDAC, 2007, pp. 250--255.
[10]
M. Pan, Y. Xu, Y. Zhang and C. Chu, "FastRoute: An Efficient and High-Quality Global Router", ACM VLSI Design, 2012, pp. 14:1--14:1.
[11]
H. Shin, C. King and C. Hu, "Thin Oxide Damage by Plasma Etching and Ashing Processes", Proc. IRPS, 1992, pp. 37--41
[12]
Y. Xu, Y. Zhang and C. Chu, "FastRoute 4.0: Global Router with Efficient Via Minimization", Proc. ASPDAC, 2009, pp. 576--581.
[13]
Y. Zhang, Y. Xu and C. Chu, "FastRoute 3.0: A Fast and High Quality Global Router Based on Virtual Capacity", IEEE/ACM ICCAD, 2008, pp. 344--349.
[14]
B. Hendrickson and R. Leland, "The Chaco User's Guide", https://prodng.sandia.gov/techlib-noauth/access-control.cgi/1995/952344.pdf
[15]
FastRoute, http://home.eng.iastate.edu/~cnchu/FastRoute.html
[16]
G. Karypis and V. Kumar, "METIS - Unstructured Graph Partitioning and Sparse Matrix Ordering System, V. 2.0", https://dm.kaist.ac.kr/kse625/resources/metis.pdf
[17]
OpenDB, https://github.com/The-OpenROAD-Project/OpenDB
[18]
OpenROAD, https://github.com/The-OpenROAD-Project/OpenROAD
[19]
The OpenROAD flow, https://github.com/The-OpenROAD-Project/OpenROAD-flow
[20]
TritonRoute, https://github.com/The-OpenROAD-Project/TritonRoute
[21]
Yosys, https://github.com/The-OpenROAD-Project/yosys
- Contributions to openroad from abroad: experiences and learnings
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Published: 17 December 2020
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