research-article

Flexible chip placement via reinforcement learning: late breaking results

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Tung-Chieh ChenAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1392 - 1393

https://doi.org/10.1145/3489517.3530617

Published: 23 August 2022 Publication History

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Abstract

Recently, successful applications of reinforcement learning to chip placement have emerged. Pretrained models are necessary to improve efficiency and effectiveness. Currently, the weights of objective metrics (e.g., wirelength, congestion, and timing) are fixed during pretraining. However, fixed-weighed models cannot generate the diversity of placements required for engineers to accommodate changing requirements as they arise. This paper proposes flexible multiple-objective reinforcement learning (MORL) to support objective functions with inference-time variable weights using just a single pretrained model. Our macro placement results show that MORL can generate the Pareto frontier of multiple objectives effectively.

References

[1]

D. Silver, A. Huang, C. J. Maddison et al., "Mastering the game of Go with deep neural networks and tree search," Nature, vol. 529, no. 7587, pp. 484--489, Jan. 2016.

Crossref

Google Scholar

[2]

H. van Seijen, M. Fatemi, J. Romoff et al., "Hybrid reward architecture for reinforcement learning," 2017, arXiv:1706.04208.

Google Scholar

[3]

S. Khadka and K. Tumer, "Evolution-guided policy gradient in reinforcement learning," 2018, arXiv:1805.07917.

Google Scholar

[4]

A. Mirhoseini, A. Goldie, M. Yazgan et al., "A graph placement methodology for fast chip design," Nature, vol. 594, no. 7862, pp. 207--212, 2021.

Crossref

Google Scholar

[5]

J. Schulman, P. Moritz, S. Levine et al., "High-dimensional continuous control using generalized advantage estimation," International Conference on Learning Representations, 2015.

Google Scholar

[6]

J. Schulman, F. Wolski, P. Dhariwal et al., "Proximal policy optimization algorithms," 2017, arXiv:1707.06347.

Google Scholar

[7]

R. Yang, X. Sun, and K. Narasimhan, "A generalized algorithm for multi-objective reinforcement learning and policy adaptation," 2019, arXiv:1908.08342.

Google Scholar

[8]

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: applications in VLSI domain," IEEE Trans. VLSI Syst., vol. 7, no. 1, pp. 69--79, 1999.

Digital Library

Google Scholar

[9]

C.-C. Huang, H.-Y. Lee, B.-Q. Lin et al., "NTUplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 37, no. 3, pp. 669--681, 2018.

Crossref

Google Scholar

[10]

Y. Lin, Z. Jiang, J. Gu et al., "DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 40, no. 4, pp. 748--761, 2021.

Crossref

Google Scholar

[11]

K.-R. Dai, W.-H. Liu, and Y.-L. Li, "NCTU-GR: efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-D global routing," IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 3, pp. 459--472, 2012.

Digital Library

Google Scholar

[12]

M.-C. Kim, J. Hu, J. Li, and N. Viswanathan, "ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite," in ICCAD, 2015.

Digital Library

Google Scholar

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Bai YYi EXing WYu BJin ZDe V(2024)Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and ProjectionProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658467(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658467
Tseng IHui-Ru Jiang IPosser G(2024)Challenges in Floorplanning and Macro Placement for Modern SoCsProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3639695(71-72)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3639695
Lee PChen T(2024)AI-Driven Innovations in IC Designs: From Planning to Implementation2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)10.1109/VLSITSA60681.2024.10546365(1-2)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VLSITSA60681.2024.10546365
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Published In

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Bai YYi EXing WYu BJin ZDe V(2024)Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and ProjectionProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658467(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658467
Tseng IHui-Ru Jiang IPosser G(2024)Challenges in Floorplanning and Macro Placement for Modern SoCsProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3639695(71-72)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3639695
Lee PChen T(2024)AI-Driven Innovations in IC Designs: From Planning to Implementation2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)10.1109/VLSITSA60681.2024.10546365(1-2)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VLSITSA60681.2024.10546365
Sadrafshari MDobre OZhang L(2024)Reinforcement-Learning-Based Foggy-Aware Optimal Placement Method for Analog and MixedSignal Circuits2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558520(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558520
Goldie AMirhoseini AYazgan MJiang JSonghori EWang SLee YJohnson EPathak ONova APak JTong ASrinivasa KHang WTuncer ELe QLaudon JHo RCarpenter RDean J(2024)Addendum: A graph placement methodology for fast chip designNature10.1038/s41586-024-08032-5634:8034(E10-E11)Online publication date: 26-Sep-2024
https://doi.org/10.1038/s41586-024-08032-5

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