research-article

An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling

Authors:

Xuan ZengAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 625 - 630

https://doi.org/10.1145/3489517.3530514

Published: 23 August 2022 Publication History

Abstract

This paper presents an efficient yield optimization method for analog circuits via Gaussian process classification and varying-sigma sampling. To quickly determine the better design, yield estimations are executed at varying sigma of process variations. Instead of regression methods requiring accurate yield values, a Gaussian process classification method is applied to model these preference information of designs with binary comparison results, and the preferential Bayesian optimization framework is implemented to guide the search. Additionally, a multi-fidelity surrogate model is adopted to learn the yield correlation at different sigmas. Compared with the state-of-the-art methods, the proposed method achieves up to 12× speed-up without loss of accuracy.

References

[1]

Manuel Barros, Jorge Guilherme, and Nuno Horta. 2010. Analog circuits optimization based on evolutionary computation techniques. Integration, the VLSI Journal 43, 1 (2010), 136--155.

Digital Library

[2]

Shubhankar Basu, Balaji Kommineni, and Ranga Vemuri. 2009. Variation-aware macromodeling and synthesis of analog circuits using spline center and range method and dynamically reduced design space. In Proc. VLSI Design. IEEE, 433--438.

Digital Library

[3]

Olivier Chapelle and Lihong Li. 2011. An empirical evaluation of thompson sampling. In Proc. NIPS. 2249--2257.

[4]

Wei Chu and Zoubin Ghahramani. 2005. Preference learning with Gaussian processes. In Proc. ICML. 137--144.

Digital Library

[5]

Javier González, Zhenwen Dai, Andreas Damianou, and Neil D Lawrence. 2017. Preferential bayesian optimization. In icml. PMLR, 1282--1291.

[6]

Helmut E Graeb. 2007. Analog design centering and sizing. Vol. 64. Springer.

[7]

Ivick Guerra-Gomez, Esteban Tlelo-Cuautle, and Luis Gerardo de la Fraga. 2015. OCBA in the yield optimization of analog integrated circuits by evolutionary algorithms. In Proc. ISCAS. IEEE, 1933--1936.

[8]

Donald R Jones, Matthias Schonlau, and William J Welch. 1998. Efficient global optimization of expensive black-box functions. Journal of Global Optimization 13, 4 (1998), 455--492.

Digital Library

[9]

Bo Liu, Francisco V Fernández, and Georges GE Gielen. 2011. Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE TCAD 30, 6 (2011), 793--805.

[10]

Saraju P. Mohanty and Elias Kougianos. 2014. Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs. IEEE TSM 27, 1 (2014), 22--31.

[11]

O. Okobiah, S. Mohanty, and E. Kougianos. 2014. Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study. IEEE TVLSI 22, 4 (2014), 932--937.

[12]

Paris Perdikaris, Maziar Raissi, Andreas Damianou, ND Lawrence, and George Em Karniadakis. 2017. Nonlinear information fusion algorithms for data-efficient multi-fidelity modelling. Proc. R. Soc. A 473, 2198 (2017), 20160751.

[13]

Robert Schwencker, Frank Schenkel, Michael Pronath, and H Graeb. 2002. Analog circuit sizing using adaptive worst-case parameter sets. In Proc. DATE. IEEE, 581--585.

[14]

Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, and Jianjun Cheng. 2005. Application-specific worst case corners using response surfaces and statistical models. IEEE TCAD 24, 9 (2005), 1372--1380.

[15]

Bobak Shahriari, Kevin Swersky, Ziyu Wang, Ryan P Adams, and Nando De Freitas. 2015. Taking the human out of the loop: A review of Bayesian optimization. Proc. IEEE 104, 1 (2015), 148--175.

[16]

Jasper Snoek, Hugo Larochelle, and Ryan P Adams. 2012. Practical bayesian optimization of machine learning algorithms. In Proc. NIPS. 2951--2959.

[17]

Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, and Ben Gu. 2015. Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space. IEEE TCAD 34, 7 (2015), 1096--1109.

Digital Library

[18]

Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, and Xuan Zeng. 2018. Efficient yield optimization for analog and sram circuits via gaussian process regression and adaptive yield estimation. IEEE TCAD 37, 10 (2018), 1929--1942.

Digital Library

[19]

Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, and Xiangdong Hu. 2017. Efficient Bayesian yield optimization approach for analog and SRAM circuits. In Proc. DAC. IEEE, 1--6.

Digital Library

[20]

Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng. 2020. An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. In Proc. DAC. IEEE, 1--6.

[21]

Dennis D. Weller, Michael Hefenbrock, Michael Beigl, and Mehdi B. Tahoori. 2021. Fast and Efficient High-Sigma Yield Analysis and Optimization using Kernel Density Estimation on a Bayesian Optimized Failure Rate Model. IEEE TCAD (2021), 1--1.

[22]

Christopher KI Williams and Carl Edward Rasmussen. 2006. Gaussian processes for machine learning. Vol. 2. MIT press Cambridge, MA.

[23]

Shuhan Zhang, Fan Yang, Dian Zhou, and Xuan Zeng. 2020. Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. In Proc. ASPDAC. IEEE, 440--445.

Digital Library

Cited By

Chae HZhu KMutnury BJiang Zde Araujo DWallace DWinterberg DKlivans APan DKim T(2024)ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package Using Machine LearningProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473886(644-650)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473886
Qiu YHuang TTang YLiu YKong YYu XZeng XFan Y(2023)Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce ErrorsIEEE Transactions on Computers10.1109/TC.2023.334767573:3(902-914)Online publication date: 27-Dec-2023
https://dl.acm.org/doi/10.1109/TC.2023.3347675

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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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National Natural Science Foundation of China (NSFC) research projects
National Key R\&D Program of China

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DAC '22

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Cited By

Chae HZhu KMutnury BJiang Zde Araujo DWallace DWinterberg DKlivans APan DKim T(2024)ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package Using Machine LearningProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473886(644-650)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473886
Qiu YHuang TTang YLiu YKong YYu XZeng XFan Y(2023)Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce ErrorsIEEE Transactions on Computers10.1109/TC.2023.334767573:3(902-914)Online publication date: 27-Dec-2023
https://dl.acm.org/doi/10.1109/TC.2023.3347675

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