research-article

Public Access

MOESI-prime: preventing coherence-induced hammering in commodity workloads

Authors:

Kevin Loughlin,

Yatin A. Manerkar,

Baris KasikciAuthors Info & Claims

ISCA '22: Proceedings of the 49th Annual International Symposium on Computer Architecture

Pages 670 - 684

https://doi.org/10.1145/3470496.3527427

Published: 11 June 2022 Publication History

Abstract

Prior work shows that Rowhammer attacks---which flip bits in DRAM via frequent activations of the same row(s)---are viable. Adversaries typically mount these attacks via instruction sequences that are carefully-crafted to bypass CPU caches. However, we discover a novel form of hammering that we refer to as coherence-induced hammering, caused by Intel's implementations of cache coherent non-uniform memory access (ccNUMA) protocols. We show that this hammering occurs in commodity benchmarks on a major cloud provider's production hardware, the first hammering found to be generated by non-malicious code. Given DRAM's rising susceptibility to bit flips, it is paramount to prevent coherence-induced hammering to ensure reliability and security in the cloud.

Accordingly, we introduce MOESI-prime, a ccNUMA coherence protocol that mitigates coherence-induced hammering while retaining Intel's state-of-the-art scalability. MOESI-prime shows that most DRAM reads and writes triggering such hammering are unnecessary. Thus, by encoding additional information in the coherence protocol, MOESI-prime can omit these reads and writes, preventing coherence-induced hammering in non-malicious and malicious workloads. Furthermore, by omitting unnecessary reads and writes, MOESI-prime has negligible effect on average performance (within ±0.61% of MESI and MOESI) and average DRAM power (0.03%-0.22% improvement) across evaluated ccNUMA configurations.

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Cited By

Chacon GWilliams CKnechtel JSinanoglu OGratz PSoteriou V(2024)Coherence Attacks and Countermeasures in Interposer-based Chiplet SystemsACM Transactions on Architecture and Code Optimization10.1145/363346121:2(1-25)Online publication date: 15-Feb-2024
https://dl.acm.org/doi/10.1145/3633461
Li MBu KMiao CRen K(2024)TreasureCache: Hiding Cache Evictions Against Side-Channel AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2024.3354991(1-15)Online publication date: 2024
https://doi.org/10.1109/TDSC.2024.3354991
Jaleel ASaileshwar GKeckler SQureshi M(2024)PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00087(1157-1172)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00087
Show More Cited By

Index Terms

MOESI-prime: preventing coherence-induced hammering in commodity workloads
1. Security and privacy
  1. Security in hardware
  2. Systems security

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Published In

cover image ACM Conferences

ISCA '22: Proceedings of the 49th Annual International Symposium on Computer Architecture

June 2022

1097 pages

ISBN:9781450386104

DOI:10.1145/3470496

General Chairs:
Valentina Salapura
Google
,
Mohamed Zahran
New York University
,
Program Chairs:
Fred Chong
The University of Chicago
,
Lingjia Tang
The University of Michigan

Copyright © 2022 ACM.

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Published: 11 June 2022

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ISCA '22

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SIGARCH

ISCA '22: The 49th Annual International Symposium on Computer Architecture

June 18 - 22, 2022

New York, New York

Acceptance Rates

ISCA '22 Paper Acceptance Rate 67 of 400 submissions, 17%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

Chacon GWilliams CKnechtel JSinanoglu OGratz PSoteriou V(2024)Coherence Attacks and Countermeasures in Interposer-based Chiplet SystemsACM Transactions on Architecture and Code Optimization10.1145/363346121:2(1-25)Online publication date: 15-Feb-2024
https://dl.acm.org/doi/10.1145/3633461
Li MBu KMiao CRen K(2024)TreasureCache: Hiding Cache Evictions Against Side-Channel AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2024.3354991(1-15)Online publication date: 2024
https://doi.org/10.1109/TDSC.2024.3354991
Jaleel ASaileshwar GKeckler SQureshi M(2024)PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00087(1157-1172)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00087
Bostanci FYüksel IOlgun AKanellopoulos KTuğrul YYağliçi ASadrosadati MMutlu O(2024)CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00050(593-612)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00050
Yağlıkçı ATuğrul YOliveira GYüksel İOlgun ALuo HMutlu O(2024)Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00048(560-577)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00048
Olgun AOsseiran MYağlıkçı ATuğrul YLuo HRhyner SSalami BLuna JMutlu O(2024)Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58291.2024.00022(75-89)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN58291.2024.00022
Orosa LRührmair UGiray Yağlikçi ALuo HOlgun AJattke PPatel MKim JRazavi KMutlu O(2024)SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature VariationsIEEE Access10.1109/ACCESS.2024.340938912(80986-81003)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3409389
Woo JSaileshwar GNair P(2023)Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10070999(374-389)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10070999
Uma VMarimuthu R(2023)D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor systemMicroelectronics Journal10.1016/j.mejo.2022.105675132:COnline publication date: 1-Feb-2023
https://dl.acm.org/doi/10.1016/j.mejo.2022.105675

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