research-article

LightPC: hardware and software co-design for energy-efficient full system persistence

Authors:

Myoungsoo JungAuthors Info & Claims

ISCA '22: Proceedings of the 49th Annual International Symposium on Computer Architecture

Pages 289 - 305

https://doi.org/10.1145/3470496.3527397

Published: 11 June 2022 Publication History

Abstract

We propose LightPC, a lightweight persistence-centric platform to make the system robust against power loss. LightPC consists of hardware and software subsystems, each being referred to as open-channel PMEM (OC-PMEM) and persistence-centric OS (PecOS). OC-PMEM removes physical and logical boundaries in drawing a line between volatile and nonvolatile data structures by unshackling new memory media from conventional PMEM complex. PecOS provides a single execution persistence cut to quickly convert the execution states to persistent information in cases of a power failure, which can eliminate persistent control overhead. We prototype LightPC's computing complex and OC-PMEM using our custom system board. PecOS is implemented based on Linux 4.19 and Berkeley bootloader on the hardware prototype. Our evaluation results show that OC-PMEM can make user-level performance comparable with a DRAM-only non-persistent system, while consuming 73% lower power and 69% less energy. LightPC also shortens the execution time of diverse HPC, SPEC, and In-memory DB workloads, compared to traditional persistent systems by 4.3X, on average.

References

[1]

S. Di, H. Guo, R. Gupta, E. R. Pershey, M. Snir, and F. Cappello, "Exploring properties and correlations of fatal events in a large-scale hpc system," IEEE Transactions on Parallel and Distributed Systems, 2018.

[2]

Y. Yin, J. Wu, X. Zhou, L. Eeckhout, A. Qouneh, T. Li, and Z. Yu, "Copa: Highly cost-effective power back-up for green datacenters," IEEE Transactions on Parallel and Distributed Systems, 2019.

[3]

M. Chtepen, F. H. Claeys, B. Dhoedt, F. De Turck, P. Demeester, and P. A. Vanrolleghem, "Adaptive task checkpointing and replication: Toward efficient fault-tolerant grids," IEEE Transactions on Parallel and Distributed Systems (TPDS'08), 2008.

[4]

S. Di, Y. Robert, F. Vivien, D. Kondo, C.-L. Wang, and F. Cappello, "Optimization of cloud task processing with checkpoint-restart mechanism," in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2013.

[5]

B. Nicolae and F. Cappello, "Blobcr: efficient checkpoint-restart for hpc applications on iaas clouds using virtual disk image snapshots," in SC'11: Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, IEEE, 2011.

[6]

R. Garg, G. Price, and G. Cooperman, "Mana for mpi: Mpi-agnostic network-agnostic transparent checkpointing," in Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing, 2019.

Digital Library

[7]

S. Kannan, A. Gavrilovska, K. Schwan, and D. Milojicic, "Optimizing checkpoints using nvm as virtual memory," in 2013 IEEE 27th International Symposium on Parallel and Distributed Processing (IPDPS'13), IEEE, 2013.

[8]

A. J. Oliner, R. K. Sahoo, J. E. Moreira, and M. Gupta, "Performance implications of periodic checkpointing on large-scale cluster systems," in 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05), IEEE, 2005.

[9]

Y. Tian, S. Klasky, H. Abbasi, J. Lofstead, R. Grout, N. Podhorszki, Q. Liu, Y. Wang, and W. Yu, "Edo: improving read performance for scientific applications through elastic data organization," in 2011 IEEE International Conference on Cluster Computing (CLUSTER'11), IEEE, 2011.

[10]

D. Tiwari, S. Gupta, and S. S. Vazhkudai, "Lazy checkpointing: Exploiting temporal locality in failures to mitigate checkpointing overheads on extreme-scale systems," in 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, IEEE, 2014.

[11]

J. Cao, K. Arya, R. Garg, S. Matott, D. K. Panda, H. Subramoni, J. Vienne, and G. Cooperman, "Systemlevel scalable checkpoint-restart for petascale computing," in 2016 IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS'16), IEEE, 2016.

[12]

L. A. B. Gomez, N. Maruyama, F. Cappello, and S. Matsuoka, "Distributed diskless checkpoint for large scale systems," in 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing (CCGRID'10), IEEE, 2010.

[13]

Intel, "Optane DC Persistent Memory." https://www.intel.com/content/www/us/en/architecture-and-technology/optane-dc-persistent-memory.html.

[14]

N. Tanabe and T. Endo, "Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache," in Proceedings of the 2nd International Conference on High Performance Compilation, Computing and Communications (HP3C'18), 2018.

[15]

B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, "Phase-change technology and the future of main memory," IEEE micro, 2010.

[16]

M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in Proceedings of the 36th annual international symposium on Computer architecture, 2009.

[17]

H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase change memory," Proceedings of the IEEE, 2010.

[18]

T. Mason, T. D. Doudali, M. Seltzer, and A. Gavrilovska, "Unexpected performance of intel® optane® dc persistent memory," IEEE Computer Architecture Letters, 2020.

[19]

Z. Wang, X. Liu, J. Yang, T. Michailidis, S. Swanson, and J. Zhao, "Characterizing and modeling non-volatile memory systems," in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), IEEE, 2020.

[20]

S. Gugnani, A. Kashyap, and X. Lu, "Understanding the idiosyncrasies of real persistent memory," Proceedings of the VLDB Endowment, 2020.

[21]

L. Zhang and S. Swanson, "Pangolin: A fault-tolerant persistent memory programming library," in 2019 USENIX Annual Technical Conference (USENIXATC 19), 2019.

[22]

A. Demeri, W.-H. Kim, R. M. Krishnan, J. Kim, M. Ismail, and C. Min, "Poseidon: Safe, fast and scalable persistent memory allocator," in Proceedings of the 21st International Middleware Conference, 2020.

[23]

J. Xu, L. Zhang, A. Memaripour, A. Gangadharaiah, A. Borase, T. Brito Da Silva, S. Swanson, and A. Rudoff, "Nova-fortis: A fault-tolerant non-volatile main memory file system," in Proceedings of the 26th Symposium on Operating Systems Principles (SOSP '17), ACM, 2017.

[24]

Q. Hu, J. Ren, A. Badam, J. Shu, and T. Moscibroda, "Log-structured non-volatile main memory," in 2017 USENIX Annual Technical Conference (USENIXATC 17), 2017.

[25]

SiFive, "SiFive TileLink Specification." https://sifive.cdn.prismic.io/sifive/7bef6f5c-ed3a-4712-866a-1a2e0c6b7b13_tilelink_spec_1.8.1.pdf.

[26]

J. Izraelevitz, J. Yang, L. Zhang, J. Kim, X. Liu, A. Memaripour, Y. J. Soh, Z. Wang, Y. Xu, S. R. Dulloor, et al., "Basic performance measurements of the intel optane dc persistent memory module," arXiv preprint arXiv:1903.05714, 2019.

[27]

J. Yang, J. Kim, M. Hoseinzadeh, J. Izraelevitz, and S. Swanson, "An empirical guide to the behavior and use of scalable persistent memory," in 18th USENIX Conference on File and Storage Technologies (FAST 20), 2020.

[28]

"Quick start guide part 1: Persistent memory provisioning introduction." https://software.intel.com/content/www/us/en/develop/articles/qsg-intro-to-provisioning-pmem.html.

[29]

N. AbouGhazaleh, B. R. Childers, D. Mossé, and R. G. Melhem, "Near-memory caching for improved energy consumption," IEEE Transactions on Computers, 2007.

Digital Library

[30]

B. Nale, R. K. Ramanujan, M. P. Swaminathan, T. Thomas, and T. Polepeddi, "Memory channel that supports near memory and far memory access," May 17 2016. US Patent 9,342,453.

[31]

"Direct access for files." https://www.kernel.org/doc/Documentation/filesystems/dax.txt.

[32]

R. Kateja, N. Beckmann, and G. R. Ganger, "Tvarak: software-managed hardware offload for redundancy in direct-access nvm storage," in 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), IEEE, 2020.

[33]

Intel, "libpmemobj: A native transactional object store." https://pmem.io/pmdk/libpmemobj/.

[34]

Intel, "Pmdk: Persistent memory development kit." http://www.pmem.io.

[35]

O. Krieger, M. Auslander, B. Rosenburg, R. W. Wisniewski, J. Xenidis, D. Da Silva, M. Ostrowski, J. Ap-pavoo, M. Butrico, M. Mergen, et al., "K42: building a complete operating system," ACM SIGOPS Operating Systems Review, 2006.

Digital Library

[36]

D. Bittman, P. Alvaro, P. Mehra, D. D. Long, and E. L. Miller, "Twizzler: a data-centric os for non-volatile memory," in 2020 USENIX Annual Technical Conference (USENIXATC 20), 2020.

[37]

J. Hiller, J. Amann, and O. Hohlfeld, "The boon and bane of cross-signing: Shedding light on a common practice in public key infrastructures," in Proceedings of the 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020.

[38]

M. A. Heroux, D. W. Doerfler, P. S. Crozier, J. M. Willenbring, H. C. Edwards, A. Williams, M. Rajan, E. R. Keiter, H. K. Thornquist, and R. W. Numrich, "Improving performance via mini-applications," Sandia National Laboratories, Tech. Rep. SAND2009--5574, 2009.

[39]

R. J. Zerr and R. S. Baker, "Snap: Sn (discrete ordinates) application proxy," Online: https://github.com/losalamos/SNAP. Accessed: Sep, 2014.

[40]

U. M. Yang et al., "Boomeramg: a parallel algebraic multigrid solver and preconditioner," Applied Numerical Mathematics, 2002.

[41]

A. Phansalkar, A. Joshi, and L. K. John, "Analysis of redundancy and application balance in the spec cpu2006 benchmark suite," in Proceedings of the 34th annual international symposium on Computer architecture, 2007.

[42]

J. Treibig, G. Hager, and G. Wellein, "Likwid: A lightweight performance-oriented tool suite for x86 multicore environments," in 2010 39th International Conference on Parallel Processing Workshops (ICPP'10), IEEE, 2010.

[43]

B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable dram alternative," in Proceedings of the 36th annual international symposium on Computer architecture, 2009.

[44]

Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, "A case for exploiting subarray-level parallelism (salp) in dram," in 2012 39th Annual International Symposium on Computer Architecture (ISCA), IEEE, 2012.

[45]

J. Zhao, B. Korpan, A. Gonzalez, and K. Asanovic, "Sonicboom: The 3rd generation berkeley out-of-order machine," May 2020.

[46]

"Xilinx virtex7 fpga." https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html.

[47]

S. flower, "Super flower SF-600R12A." https://www.super-flower.com.

[48]

DELL, "DELL Power Supply 770-BCBD." https://www.dell.com/en-sg/work/shop/dell-mellanox-sb7800-sb7890-460-watt-power-supply/apd/770-bcbd/computer-chassis-components.

[49]

"Device power management specification." https://elinux.org/Device_Power_Management_Specification.

[50]

ARM, "AMBA AXI and ACE protocol specification." https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf.

[51]

H. T. Consortium et al., "Hypertransport i," O Link Specification, 2003.

[52]

"Introduction to intel® architecture." https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-introduction-basics-paper.pdf.

[53]

M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, "Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling," in 2009 42nd Annual IEEE/ACM international symposium on microarchitecture (MICRO), IEEE, 2009.

[54]

M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano, "Improving read performance of phase change memories via write cancellation and write pausing," in HPCA-16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, IEEE, 2010.

[55]

X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, "Hybrid cache architecture with disparate memory technologies," ACM SIGARCH computer architecture news, 2009.

[56]

M. Le Gallo and A. Sebastian, "An overview of phase-change memory device physics," Journal of Physics D: Applied Physics, 2020.

[57]

P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," ACM SIGARCH computer architecture news, 2009.

[58]

K. Kim, S.-W. Lee, B. Moon, C. Park, and J.-Y. Hwang, "Ipl-p: In-page logging with pcram," Proceedings of the VLDB Endowment, 2011.

[59]

W. R. Dieter and J. E. Lumpp Jr, "User-level check-pointing for linuxthreads programs.," in USENIX Annual Technical Conference, FREENIX Track, 2001.

[60]

P. H. Hargrove and J. C. Duell, "Berkeley lab checkpoint/restart (blcr) for linux clusters," in Journal of Physics: Conference Series, IOP Publishing, 2006.

[61]

Y. Choi, I. Song, M.-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, et al., "A 20nm 1.8 v 8gb pram with 40mb/s program bandwidth," in 2012 IEEE International Solid-State Circuits Conference, IEEE, 2012.

[62]

"Redis." https://redis.io/.

[63]

"Keydb." https://keydb.dev/.

[64]

"Memcached." https://memcached.org/.

[65]

"Sqlite." https://www.sqlite.org/.

[66]

J. Zhao, B. Korpan, A. Gonzalez, and K. Asanovic, "Sonicboom: The 3rd generation berkeley out-of-order machine," in Fourth Workshop on Computer Architecture Research with RISC-V, 2020.

[67]

S.-J. Cho, J. Ahn, H. Choi, and W. Sung, "Performance analysis of multi-bank dram with increased clock frequency," in 2012 IEEE International Symposium on Circuits and Systems, IEEE, 2012.

[68]

J. D. McCalpin, "Stream benchmark," Link: www.cs.virginia.edu/stream/ref. html# what, 1995.

[69]

K. Maeng and B. Lucia, "Adaptive dynamic checkpointing for safe efficient intermittent computing," in 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI'18), 2018.

[70]

Y. Zhang and K. Chakrabarty, "Energy-aware adaptive checkpointing in embedded real-time systems," in Proceedings of the conference on Design, Automation and Test in Europe-Volume 1, IEEE Computer Society, 2003.

[71]

J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson, "Nv-heaps: making persistent objects fast and safe with next-generation, non-volatile memories," in Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11), ACM, 2011.

[72]

K. Ma, Y. Zheng, S. Li, K. Swaminathan, X. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan, "Architecture exploration for ambient energy harvesting nonvolatile processors," in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA'15), IEEE, 2015.

[73]

F. Su, K. Ma, X. Li, T. Wu, Y. Liu, and V. Narayanan, "Nonvolatile processors: Why is it trending?," in Design, Automation Test in Europe Conference Exhibition (DATE), 2017, IEEE, 2017.

[74]

Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M.-F. Chiang, Y. Yan, B. Sai, and H. Yang, "A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops," in 2012 Proceedings of the ESSCIRC (ESSCIRC'12), IEEE, 2012.

[75]

J. Xu and S. Swanson, "Nova: A log-structured file system for hybrid volatile/non-volatile main memories," in Proceedings of the 14th USENIX Conference on File and Storage Technologies (FAST '16), USENIX, 2016.

[76]

D. Kim, S. Lee, J. Chung, D. H. Kim, D. H. Woo, S. Yoo, and S. Lee, "Hybrid dram/pram-based main memory for single-chip cpu/gpu," in DAC Design Automation Conference 2012, IEEE, 2012.

[77]

B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable dram alternative," ACM SIGARCH Computer Architecture News, 2009.

Digital Library

[78]

V. Leonov, "Energy harvesting for self-powered wearable devices," in Wearable Monitoring Systems, Springer, 2011.

[79]

D. Narayanan and O. Hodson, "Whole-system persistence," in Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '12), ACM, 2012.

[80]

B. K. Kim, S. Sy, A. Yu, and J. Zhang, "Electrochemical supercapacitors for energy storage and conversion," Handbook of Clean Energy Systems, 2015.

[81]

"2021. intel optane persistent memory 200 series brief." https://www.intel.com/content/www/us/en/products/docs/memory-storage/optane-persistent-memory/optane-persistent-memory-200-series-brief.html.

[82]

H.-Y. Cheng, F. Carta, W.-C. Chien, H.-L. Lung, and M. J. BrightSky, "3d cross-point phase-change memory for storage-class memory," Journal of Physics D: Applied Physics, vol. 52, no. 47, p. 473002, 2019.

[83]

P. G. Emma, W. R. Reohr, and M. Meterelliyoz, "Rethinking refresh: Increasing availability and reducing power in dram for cache applications," IEEE micro, vol. 28, no. 6, pp. 47--56, 2008.

Digital Library

[84]

S.-L. Lu, Y.-C. Lin, and C.-L. Yang, "Improving dram latency with dynamic asymmetric subarray," in 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 255--266, IEEE, 2015.

[85]

H. Aziza, M. Moreau, M. Fieback, M. Taouil, and S. Hamdioui, "An energy-efficient current-controlled write and read scheme for resistive rams (rrams)," IEEE Access, vol. 8, pp. 137263--137274, 2020.

[86]

W. Kim, M. BrightSky, T. Masuda, N. Sosa, S. Kim, R. Bruce, F. Carta, G. Fraczak, H. Cheng, A. Ray, et al., "Ald-based confined pcm with a metallic liner toward unlimited endurance," in 2016 IEEE International Electron Devices Meeting (IEDM), pp. 4--2, IEEE, 2016.

[87]

S. Lee, M. Kim, G. Do, S. Kim, H. Lee, J. Sim, N. Park, S. Hong, Y. Jeon, K. Choi, et al., "Programming disturbance and cell scaling in phase change memory: For up to 16nm based 4f 2 cell," in 2010 Symposium on VLSI Technology, pp. 199--200, IEEE, 2010.

[88]

R. Wang, L. Jiang, Y. Zhang, and J. Yang, "Sd-pcm: Constructing reliable super dense phase change memory under write disturbance," ACM SIGARCH Computer Architecture News, vol. 43, no. 1, pp. 19--31, 2015.

Digital Library

[89]

M. K. Tavana and D. Kaeli, "Cost-effective write disturbance mitigation techniques for advancing pcm density," in 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 253--260, IEEE, 2017.

[90]

S. W. Fong, C. M. Neumann, and H.-S. P. Wong, "Phase-change memory---towards a storage-class memory," IEEE Transactions on Electron Devices, 2017.

[91]

G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, et al., "Phase change memory technology," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 28, no. 2, pp. 223--262, 2010.

[92]

Y. Xie, W. Kim, Y. Kim, S. Kim, J. Gonsalves, M. BrightSky, C. Lam, Y. Zhu, and J. J. Cha, "Self-healing of a confined phase change memory device with a metallic surfactant layer," Advanced Materials, vol. 30, no. 9, p. 1705587, 2018.

[93]

J. Kong and H. Zhou, "Improving privacy and lifetime of pcm-based main memory," in 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN), pp. 333--342, IEEE, 2010.

[94]

A. Devices, "Bios and kernel developer's guide (bkdg) for amd family 15h models 00h-0fh processors (2012)," URL https://www.amd.com/system/files/Tech-Docs/42301_15h_Mod_00h-0Fh_BKDG.pdf.

[95]

I. X. Processor, "E7 family: Reliability, availability, and serviceability," 2012.

[96]

H. P. Enterprise, "How memory ras technologies can enhance the uptime of hpe proliant servers," 2016.

[97]

H.-M. Chen, S.-Y. Lee, T. Mudge, C.-J. Wu, and C. Chakrabarti, "Configurable-ecc: Architecting a flexible ecc scheme to support different sized accesses in high bandwidth memory systems," IEEE Transactions on Computers, vol. 68, no. 5, pp. 646--659, 2018.

[98]

T. J. Dell, "A white paper on the benefits of chipkill-correct ecc for pc server main memory," IBM Microelectronics division, vol. 11, no. 1--23, pp. 5--7, 1997.

[99]

J. Kim, M. Sullivan, and M. Erez, "Bamboo ecc: Strong, safe, and flexible codes for reliable computer memory," in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp. 101--112, IEEE, 2015.

[100]

J. Kim, M. Sullivan, S. Lym, and M. Erez, "All-inclusive ecc: Thorough end-to-end protection for reliable computer memory," in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp. 622--633, IEEE, 2016.

Cited By

Zeng JZhang TJung C(2024)Compiler-Directed Whole-System Persistence2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00074(961-977)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00074
Kwon MLee SChoi HHwang JJung M(2023)Realizing Strong Determinism Contract on Log-Structured Merge Key-Value StoresACM Transactions on Storage10.1145/358269519:2(1-29)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582695

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cover image ACM Conferences

ISCA '22: Proceedings of the 49th Annual International Symposium on Computer Architecture

June 2022

1097 pages

ISBN:9781450386104

DOI:10.1145/3470496

General Chairs:
Valentina Salapura
Google
,
Mohamed Zahran
New York University
,
Program Chairs:
Fred Chong
The University of Chicago
,
Lingjia Tang
The University of Michigan

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Cited By

Zeng JZhang TJung C(2024)Compiler-Directed Whole-System Persistence2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00074(961-977)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00074
Kwon MLee SChoi HHwang JJung M(2023)Realizing Strong Determinism Contract on Log-Structured Merge Key-Value StoresACM Transactions on Storage10.1145/358269519:2(1-29)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582695

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