research-article

Network-on-Chip Microarchitecture-based Covert Channel in GPUs

Authors:

Leila Delshadtehrani,

John KimAuthors Info & Claims

MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 565 - 577

https://doi.org/10.1145/3466752.3480093

Published: 17 October 2021 Publication History

Abstract

As GPUs are becoming widely deployed in the cloud infrastructure to support different application domains, the security concerns of GPUs are becoming increasingly important. In particular, the support for multiprogramming in modern GPUs has led to new vulnerabilities since multiple kernels in a GPU can be executed at the same time. In this work, we propose a new microarchitectural timing covert channel for GPUs that can be established based on the shared, on-chip interconnect channels. We first reverse-engineer the organization of the on-chip networks in modern GPUs to understand the core placements throughout the GPU. The hierarchical organization of the GPU results in the sharing of interconnect bandwidth between neighboring cores. Based on this understanding, we identify how contention for the interconnect bandwidth can be exploited for a novel covert channel attack. We propose two types of interconnect-based covert channels that exploit the on-chip network hierarchy. Unlike cache-based covert channels, no states of the on-chip network need to be modified for communication in our interconnect-based covert channel and the impact of contention is very predictable. By exploiting the parallelism of GPUs, our proposed covert channel results in very high bandwidth – achieving approximately 24 Mbps of bandwidth on NVIDIA Volta GPUs and results in one of the highest known microarchitectural covert channel bandwidth.

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cover image ACM Conferences

MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

October 2021

1322 pages

ISBN:9781450385572

DOI:10.1145/3466752

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Published: 17 October 2021

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Ma RHuang JZhang SXie YLuo G(2025)NoCFuzzer: Automating NoC Verification in UVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343019544:1(371-384)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3430195
Fang JCheng HWang YZhai R(2025)DRCD: a regional-contention-driven arbitration policy for CPU–GPU heterogeneous systemsThe Journal of Supercomputing10.1007/s11227-025-07001-781:3Online publication date: 9-Feb-2025
https://doi.org/10.1007/s11227-025-07001-7
Jiang QWang CBalzarotti DXu W(2024)Sync+SyncProceedings of the 33rd USENIX Conference on Security Symposium10.5555/3698900.3699088(3349-3366)Online publication date: 14-Aug-2024
https://dl.acm.org/doi/10.5555/3698900.3699088
Chen CCui JQu GZhang J(2024)Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk SynchronizationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.341425519(8066-8078)Online publication date: 2024
https://doi.org/10.1109/TIFS.2024.3414255
Miao YZhang YWu DZhang DTan GZhang RKandemir M(2024)Veiled Pathways: Investigating Covert and Side Channels Within GPU Uncore2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00088(1169-1183)Online publication date: 2-Nov-2024
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Jin ZAhn JKim JKasan HSong JSong WKim J(2024)Ghost Arbitration: Mitigating Interconnect Side-Channel Timing Attacks in GPU2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00086(1138-1152)Online publication date: 2-Nov-2024
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Jin ZRocca CKim JKasan HRhu MBakhoda AAamodt TKim J(2024)Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00070(885-898)Online publication date: 2-Nov-2024
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