research-article

A comparative survey of open-source application-class RISC-V processor implementations

Authors:

Alexander Dörflinger,

Benedikt Kleinbeck,

Harald Michalik,

Christopher Blochwitz,

Mladen BerekovicAuthors Info & Claims

CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers

Pages 12 - 20

https://doi.org/10.1145/3457388.3458657

Published: 11 May 2021 Publication History

Abstract

The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology.

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Index Terms

A comparative survey of open-source application-class RISC-V processor implementations
1. Computer systems organization
  1. Architectures
    1. Serial architectures
  2. Embedded and cyber-physical systems
    1. System on a chip

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cover image ACM Conferences

CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers

May 2021

254 pages

ISBN:9781450384049

DOI:10.1145/3457388

General Chairs:
Maurizio Palesi
University of Catania, IT
,
Antonino Tumeo
Pacific Northwest National Laboratory
,
Program Chairs:
Georgios I. Goumas
National Technical University of Athens, GR
,
Carmen G. Almudever
Delft University of Technology, NL/Technical University of Valencia (UPV), ES

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Published: 11 May 2021

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https://doi.org/10.1109/TVLSI.2024.3496858
Song YWoo BHan YKang BLuo BLiao XXu JKirda ELie D(2024)Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged SoftwareProceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security10.1145/3658644.3690247(198-212)Online publication date: 2-Dec-2024
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