research-article

Public Access

Hardware Information Flow Tracking

Authors:

Armaiti Ardeshiricham,

Ryan KastnerAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 54, Issue 4

Article No.: 83, Pages 1 - 39

https://doi.org/10.1145/3447867

Published: 03 May 2021 Publication History

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Abstract

Information flow tracking (IFT) is a fundamental computer security technique used to understand how information moves through a computing system. Hardware IFT techniques specifically target security vulnerabilities related to the design, verification, testing, manufacturing, and deployment of hardware circuits. Hardware IFT can detect unintentional design flaws, malicious circuit modifications, timing side channels, access control violations, and other insecure hardware behaviors. This article surveys the area of hardware IFT. We start with a discussion on the basics of IFT, whose foundations were introduced by Denning in the 1970s. Building upon this, we develop a taxonomy for hardware IFT. We use this to classify and differentiate hardware IFT tools and techniques. Finally, we discuss the challenges yet to be resolved. The survey shows that hardware IFT provides a powerful technique for identifying hardware security vulnerabilities, as well as verifying and enforcing hardware security properties.

References

[1]

Shan Ao and Guo Shuangzhou. 2011. An enhancement technology about system security based on dynamic information flow tracking. In Proc. Int. Conf. Artif. Intell., Manag. Sci. Elec. Commerce (AIMSEC). 6108--6111.

[2]

Armaiti Ardeshiricham, Wei Hu, and Ryan Kastner. 2017. Clepsydra: Modeling timing flows in hardware designs. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). 147--154.

[3]

Armaiti Ardeshiricham, Wei Hu, Joshua Marxen, and Ryan Kastner. 2017. Register transfer level information flow tracking for provably secure hardware design. In Proc. Des. Autom. Test Europe Conf. Exhib. (DATE). 1691--1696.

[4]

Armaiti Ardeshiricham, Yoshiki Takashima, Sicun Gao, and Ryan Kastner. 2019. VeriSketch: Synthesizing secure hardware designs with timing-sensitive information flow properties. In Proc. ACM Conf. Comp. Comm. Sec. (CCS). ACM, New York, NY, 1623--1638.

Digital Library

[5]

Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Cătălin Hriţcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, and Andrew Tolmach. 2014. A verified information-flow architecture. In Proc. SIGPLAN-SIGACT Symp. Principles Prog. Lang. (POPL). ACM, New York, NY, 165--178.

Digital Library

[6]

Jean Bacon, David Eyers, Thomas F. J.-M. Pasquier, Jatinder Singh, Ioannis Papagiannis, and Peter Pietzuch. 2014. Information flow control for secure cloud computing. IEEE Trans. Netw. Serv. Manag. 11, 1 (2014), 76--89.

[7]

Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, and Paolo Ienne. 2017. Arbitrary precision and complexity tradeoffs for gate-level information flow tracking. In Proc. Des. Autom. Conf. (DAC). 1--6.

Digital Library

[8]

Lionel Bening and Harry Foster. 2001. Principles of Verifiable RTL Design (2nd ed.). Kluwer Academic Publishers, New York, NY.

[9]

Mohammad-Mahdi Bidmeshki, Angelos Antonopoulos, and Yiorgos Makris. 2017. Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP. In Proc. Des. Autom. Test Europe Conf. Exhib. (DATE). 1703--1708.

[10]

Mohammad-Mahdi Bidmeshki, Xiaolong Guo, Raj Gautam Dutta, Yier Jin, and Yiorgos Makris. 2017. Data secrecy protection through information flow tracking in proof-carrying hardware IP—Part II: Framework Automation. IEEE Trans. Inf. Forensics Security 12, 10 (Oct. 2017), 2430--2443.

[11]

Mohammad-Mahdi Bidmeshki and Yiorgos Makris. 2015. Toward automatic proof generation for information flow policies in third-party hardware IP. In Proc. IEEE Int. Symp. Hardware Oriented Security Trust (HOST). 163--168.

[12]

Jeremy Blackstone, Wei Hu, Alric Althoff, Armaiti Ardeshiricham, Lu Zhang, and Ryan Kastner. 2020. A unified model for gate level propagation analysis. arxiv:2012.02791

[13]

James O. Bondi and Martha A. Branstad. 1989. Architectural support of fine-grained secure computing. In Comp. Sec. App. Conf. (ACSAC). 121--130.

[14]

Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, and Raoul Strackx. 2018. Foreshadow: Extracting the keys to the Intel SGX kingdom with transient out-of-order execution. In Proc. USENIX Security Symp. (USENIX Security). 991--1008.

[15]

G. Cabodi, P. Camurati, S. F. Finocchiaro, C. Loiacono, F. Savarese, and D. Vendraminetto. 2016. Secure path verification. In Proc. IEEE Int. Verification Security Workshop (IVSW). 1--6.

[16]

G. Cabodi, P. Camurati, S. F. Finocchiaro, F. Savarese, and D. Vendraminetto. 2017. Embedded systems secure path verification at the hardware/software interface. IEEE Design Test 34, 5 (Oct. 2017), 38--46.

[17]

Cadence. 2016. JasperGold Security Path Verification App. Retrieved March 7, 2021 from https://www.cadence.com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/security-path-verification-app.html.

[18]

Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruo Long Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey Goeders, Stephen Brown, and Jason Anderson. 2016. LegUp High-Level Synthesis. Springer, Cham, Switzerland, 175--190.

[19]

Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, and Evangelos Vlachos. 2008. Flexible hardware acceleration for instruction-grain program monitoring. In Proc. Int. Symp. Comp. Archit. (ISCA). IEEE, Los Alamitos, CA, 377--388.

Digital Library

[20]

Yu-Yuan Chen, Pramod A. Jamkhedkar, and Ruby B. Lee. 2012. A software-hardware architecture for self-protecting data. In Proc. ACM Conf. Comp. Comm. Sec. (CCS). ACM, New York, NY, 14--27.

[21]

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. 2017. Software-based gate-level information flow security for IoT systems. In Proc. Int. Symp. Microarchitecture (MICRO). ACM, New York, NY, 328--340.

Digital Library

[22]

Michael R. Clarkson and Fred B. Schneider. 2010. Hyperproperties. J. Comp. Security 18, 6 (2010), 1157--1210.

Digital Library

[23]

Ellis Cohen. 1977. Information transmission in computational systems. ACM SIGOPS Oper. Syst. Rev. 11, 5 (1977), 133--139.

Digital Library

[24]

Ellis S. Cohen. 1978. Information transmission in sequential programs. Foundations Sec. Comp. 151 (1978), 297--335.

[25]

Michael Dalton, Hari Kannan, and Christos Kozyrakis. 2007. Raksha: A flexible information flow architecture for software security. ACM SIGARCH Comput. Archit. News 35, 2 (June 2007), 482--493.

Digital Library

[26]

Lucas Davi, Matthias Hanreich, Debayan Paul, Ahmad-Reza Sadeghi, Patrick Koeberl, Dean Sullivan, Orlando Arias, and Yier Jin. 2015. HAFIX: Hardware-assisted flow integrity eXtension. In Proc. Des. Autom. Conf. (DAC). 1--6.

Digital Library

[27]

Onur Demir, Wenjie Xiong, Faisal Zaghloul, and Jakub Szefer. 2016. Survey of Approaches for Security Verification of Hardware/Software Systems. Report 2016/846. Cryptology ePrint Archive. https://eprint.iacr.org/2016/846.

[28]

Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, and G. Edward Suh. 2010. Flexible and efficient instruction-grained run-time monitoring using on-chip reconfigurable fabric. In Proc. Int. Symp. Microarchitecture (MICRO). 137--148.

[29]

Daniel Y. Deng and G. Edward Suh. 2012. High-performance parallel accelerator for flexible and efficient run-time monitoring. In Proc. IEEE/IFIP Int. Conf. Depend. Syst. Netw. (DSN). 1--12.

[30]

Shuwen Deng, Doğuhan Gümüşoğlu, Wenjie Xiong, Sercan Sari, Y. Serhan Gener, Corine Lu, Onur Demir, and Jakub Szefer. 2019. SecChisel framework for security verification of secure processor architectures. In Proc. Int. Workshop on Hardw. Archit. Supp. Sec. Priv. (HASP). ACM, New York, NY, Article 7, 8 pages.

Digital Library

[31]

Dorothy Elizabeth Robling Denning. 1975. Secure Information Flow in Computer Systems. Ph.D. Dissertation. West Lafayette, IN.

[32]

Dorothy Elizabeth Robling Denning. 1976. A lattice model of secure information flow. Commun. ACM 19, 5 (1976), 236--243.

Digital Library

[33]

Jack B. Dennis and Earl C. Van Horn. 1966. Programming semantics for multiprogrammed computations. Commun. ACM 9, 3 (1966), 143--155.

Digital Library

[34]

Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, and Jeyavijayan Rajendran. 2019. Hardfails: Insights into software-exploitable hardware bugs. In Proc. USENIX Security Symp. (USENIX Security). 213--230.

[35]

Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight, Benjamin C. Pierce, and Andre DeHon. 2015. Architectural support for software-defined metadata processing. ACM SIGPLAN Not. 50, 4 (March 2015), 487--502.

Digital Library

[36]

Petros Efstathopoulos, Maxwell Krohn, Steve VanDeBogart, Cliff Frey, David Ziegler, Eddie Kohler, David Mazieres, Frans Kaashoek, and Robert Morris. 2005. Labels and event processes in the Asbestos operating system. ACM SIGOPS Oper. Syst. Rev. 39, 5 (2005), 17--30.

Digital Library

[37]

Manuel Egele, Christopher Kruegel, Engin Kirda, Heng Yin, and Dawn Song. 2007. Dynamic spyware analysis. In Proc. USENIX Annual Technical Conf.

[38]

Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, and G. Edward Suh. 2017. Secure information flow verification with mutable dependent types. In Proc. Des. Autom. Conf. (DAC). 1--6.

[39]

Andrew Ferraiuolo, Rui Xu, Danfeng Zhang, Andrew C. Myers, and G. Edward Suh. 2017. Verification of a practical hardware security architecture through static information flow analysis. ACM SIGARCH Comput. Archit. News 45, 1 (April 2017), 555--568.

Digital Library

[40]

Andrew Ferraiuolo, Mark Zhao, Andrew C. Myers, and G. Edward Suh. 2018. HyperFlow: A processor architecture for nonmalleable, timing-safe information flow security. In Proc. ACM Conf. Comp. Comm. Sec. (CCS). ACM, New York, NY, 1583--1600.

[41]

Harry Foster. 2009. Applied Assertion-Based Verification: An Industry Perspective. Now Publishers Inc., Boston, MA.

[42]

Harry Foster, Adam Krolnik, and David Lacey. 2005. Specifying RTL properties. In Assertion-Based Design. Springer, Boston, MA. 61--102.

[43]

Joseph A. Goguen and Jose Meseguer. 1982. Security policies and security models. In Proc. IEEE Symp. Security Privacy. 11--20.

[44]

Mentor Graphics. 2016. Questa Secure Check—Exhaustive Verification of Secure Paths to Critical Hardware Storage. Retrieved March 7, 2021 from https://www.mentor.com/products/fv/questa-secure-check.

[45]

Xiaolong Guo, Huifeng Zhu, Yier Jin, and Xuan Zhang. 2019. When capacitors attack: Formal method driven design and detection of charge-domain Trojans. In Proc. Des. Autom. Test Europe Conf. Exhib. (DATE). 1727--1732.

[46]

Ziyad Hanna. 2013. Jasper Case Study on Formally Verifying Secure On-Chip Datapaths. Retrieved March 7, 2021 from http://www.deepchip.com/items/0524-03.html.

[47]

Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. 2017. Early SoC security validation by VP-based static information flow analysis. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). IEEE, Los Alamitos, CA, 400--407.

[48]

Ingoo Heo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent Byunghoon Kang, and Yunheung Paek. 2015. Implementing an application-specific instruction-set processor for system-level dynamic program analysis engines. ACM Trans. Des. Autom. Electron. Syst. 20, 4 (Sept. 2015), Article 53, 32 pages.

Digital Library

[49]

Wei Hu, Alric Althoff, Armaiti Ardeshiricham, and Ryan Kastner. 2016. Towards property driven hardware security. In Proc. Int. Workshop Microprocessor SOC Test Verification (MTV). 51--56.

[50]

Wei Hu, Armaiti Ardeshiricham, Mustafa S. Gobulukoglu, Xinmu Wang, and Ryan Kastner. 2018. Property specific information flow analysis for hardware security verification. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). IEEE, Los Alamitos, CA, 1--8.

Digital Library

[51]

Wei Hu, Armaiti Ardeshiricham, and Ryan Kastner. 2017. Identifying and measuring security critical path for uncovering circuit vulnerabilities. In Proc. Int. Workshop Microprocessor SOC Test Verification (MTV). IEEE, Los Alamitos, CA, 62--67.

[52]

Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, and Ryan Kastner. 2016. Imprecise security: Quality and complexity tradeoffs for hardware information flow tracking. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). 1--8.

Digital Library

[53]

Wei Hu, Baolei Mao, Jason Oberg, and Ryan Kastner. 2016. Detecting hardware Trojans with gate-level information-flow tracking. Computer 49, 8 (Aug. 2016), 44--52.

Digital Library

[54]

Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. 2014. Gate-level information flow tracking for security lattices. ACM Trans. Des. Autom. Electron. Syst. 20, 1 (Nov. 2014), Article 2, 25 pages.

Digital Library

[55]

Wei Hu, Jason Oberg, Jeremy Barrientos, Dejun Mu, and Ryan Kastner. 2013. Expanding gate level information flow tracking for multilevel security. IEEE Embedd. Syst. Lett. 5, 2 (June 2013), 25--28.

[56]

Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. 2011. An improved encoding technique for gate level information flow tracking. In Proc. Int. Workshop Logic Synthesis (IWLS).

[57]

Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. 2011. Theoretical fundamentals of gate level information flow tracking. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 30, 8 (Aug. 2011), 1128--1140.

Digital Library

[58]

Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. 2012. On the complexity of generating gate level information flow tracking logic. IEEE Trans. Inf. Forensics Security 7, 3 (June 2012), 1067--1080.

Digital Library

[59]

Wei Hu, Jason Oberg, Dejun Mu, and Ryan Kastner. 2012. Simultaneous information flow security and circuit redundancy in Boolean gates. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). ACM, New York, NY, 585--590.

Digital Library

[60]

Wei Hu, Xinmu Wang, and Dejun Mu. 2018. Security path verification through joint information flow analysis. In Proc. IEEE Asia Pacific Conf. Circ. Syst. (APCCAS). 415--418.

[61]

W. Hu, L. Wu, Y. Tai, J. Tan, and J. Zhang. 2020. A unified formal model for proving security and reliability properties. In Proc. IEEE Asian Test Symp. (ATS). 1--6.

[62]

Ted Huffmire, Shreyas Prasad, Tim Sherwood, and Ryan Kastner. 2006. Policy-driven memory protection for reconfigurable hardware. In Proc. European Conf. Research Comp. Sec.

Digital Library

[63]

Kangkook Jee, Vasileios P. Kemerlis, Angelos D. Keromytis, and Georgios Portokalidis. 2013. ShadowReplica: Efficient parallelization of dynamic data flow tracking. In Proc. ACM Conf. Comp. Comm. Sec. (CCS). ACM, New York, NY, 235--246.

Digital Library

[64]

Zhenghong Jiang, Steve Dai, G. Edward Suh, and Zhiru Zhang. 2018. High-level synthesis with timing-sensitive information flow enforcement. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). ACM, New York, NY, Article 88, 8 pages.

Digital Library

[65]

Zhenghong Jiang, Hanchen Jin, G. Edward Suh, and Zhiru Zhang. 2019. Designing secure cryptographic accelerators with information flow enforcement: A case study on AES. In Proc. Des. Autom. Conf. (DAC). ACM, New York, NY, Article 59, 6 pages.

Digital Library

[66]

Yier Jin, Xiaolong Guo, Raj Gautam Dutta, Mohammad-Mahdi Bidmeshki, and Yiorgos Makris. 2017. Data secrecy protection through information flow tracking in proof-carrying hardware IP—Part I: Framework fundamentals. IEEE Trans. Inf. Forensics Security 12, 10 (Oct. 2017), 2416--2429.

Digital Library

[67]

Yier Jin and Yiorgos Makris. 2012. Proof carrying-based information flow tracking for data secrecy protection and hardware trust. In Proc. IEEE VLSI Test Symp. (VTS). 252--257.

[68]

Yier Jin, Bo Yang, and Yiorgos Makris. 2013. Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing. In Proc. IEEE Int. Symp. Hardware Oriented Security Trust (HOST). 99--106.

[69]

Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, et al. 2017. Efficient tagged memory. In Proc. IEEE Int. Conf. Comp. Des. (ICCD). 641--648.

[70]

Hari Kannan, Michael Dalton, and Christos Kozyrakis. 2009. Decoupling dynamic information flow tracking with a dedicated coprocessor. In Proc. IEEE/IFIP Int. Conf. Depend. Syst. Netw. (DSN). 105--114.

[71]

Ryan Kastner. 2013. Circuit primitives for monitoring information flow and enabling redundancy. In Proc. Int. Conf. Hardware Software: Verification Testing (HVC). 6.

Digital Library

[72]

Ryan Kastner, Jason Oberg, Wei Hu, and Ali Irturk. 2011. Enforcing information flow guarantees in reconfigurable systems with mix-trusted IP. In Proc. Int. Conf. Engineering Reconfig. Syst. Algorithms (ERSA).

[73]

Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ACM SIGARCH Comput. Archit. News 42, 3 (2014), 361--372.

Digital Library

[74]

Gerwin Klein, Kevin Elphinstone, Gernot Heiser, June Andronick, David Cock, Philip Derrin, Dhammika Elkaduwe, et al. 2009. seL4: Formal verification of an OS kernel. In Proc. ACM SIGOPS Symp. Oper. Syst. Princip. (SOSP). ACM, New York, NY, 207--220.

Digital Library

[75]

Paul Kocher, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2018. Spectre attacks: Exploiting speculative execution. arxiv:1801.01203

[76]

Paul Kocher, Joshua Jaffe, and Benjamin Jun. 1999. Differential power analysis. In Advances in Cryptology—CRYPTO’99, Michael Wiener (Ed.). Springer, Berlin, Germany, 388--397.

[77]

Paul C. Kocher. 1996. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In Advances in Cryptology—CRYPTO’96, Neal Koblitz (Ed.). Springer, Berlin, Germany, 104--113.

[78]

Maxwell Krohn, Alexander Yip, Micah Brodsky, Natan Cliffer, M. Frans Kaashoek, Eddie Kohler, and Robert Morris. 2007. Information flow control for standard OS abstractions. ACM SIGOPS Oper. Syst. Rev. 41, 6 (2007), 321--334.

Digital Library

[79]

Butler W. Lampson. 1973. A note on the confinement problem. Commun. ACM 16, 10 (Oct. 1973), 613--615.

Digital Library

[80]

Butler W. Lampson. 1974. Protection. ACM SIGOPS Oper. Syst. Rev. 8, 1 (1974), 18--24.

Digital Library

[81]

Thao Le, Jia Di, Mark Tehranipoor, and Lei Wang. 2016. Tracking data flow at gate-level through structural checking. In Proc. Int. Great Lakes Symp. VLSI (GLSVLSI). 185--189.

Digital Library

[82]

Jinyong Lee, Ingoo Heo, Yongje Lee, and Yunheung Paek. 2015. Efficient dynamic information flow tracking on a processor with core debug interface. In Proc. Des. Autom. Conf. (DAC). 1--6.

Digital Library

[83]

Jinyong Lee, Ingoo Heo, Yongje Lee, and Yunheung Paek. 2016. Efficient security monitoring with the core debug interface in an embedded processor. ACM Trans. Des. Autom. Electron. Syst. 22, 1 (May 2016), Article 8, 29 pages.

Digital Library

[84]

Xun Li, Vineeth Kashyap, Jason K. Oberg, Mohit Tiwari, Vasanth Ram Rajarathinam, Ryan Kastner, Timothy Sherwood, Ben Hardekopf, and Frederic T. Chong. 2013. Position paper: Sapper—A language for provable hardware policy enforcement. In Proc. SIGPLAN Workshop Prog. Lang. Analysis Sec. (PLAS). ACM, New York, NY, 39--44.

[85]

Xun Li, Mohit Tiwari, Ben Hardekopf, Timothy Sherwood, and Frederic T. Chong. 2010. Secure information flow analysis for hardware design: Using the right abstraction for the job. In Proc. SIGPLAN Workshop Prog. Lang. Analysis Sec. ACM, New York, NY, Article 8, 7 pages.

[86]

Xun Li, Mohit Tiwari, Jason K. Oberg, Vineeth Kashyap, Frederic T. Chong, Timothy Sherwood, and Ben Hardekopf. 2011. Caisson: A hardware description language for secure information flow. In Proc. SIGPLAN Conf. Prog. Lang. Des. Impl. (PLDI). ACM, New York, NY, 109--120.

Digital Library

[87]

Xun Li, Mohit Tiwari, Timothy Sherwood, and Frederic T. Chong. 2010. Function flattening for lease-based, information-leak-free systems. In Proc. IEEE Int. Conf. App.-Specific Syst. Archit. Processors (ASAP). 349--352.

[88]

Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown. arxiv:1801.01207

[89]

Peter Lisherness and Kwang-Ting Cheng. 2009. An instrumented observability coverage method for system validation. In Proc. IEEE Int. High Level Des. Validation Test Workshop. 88--93.

[90]

Jed Liu, Joe Corbett-Davies, Andrew Ferraiuolo, Alexander Ivanov, Mulong Luo, G. Edward Suh, Andrew C. Myers, and Mark Campbell. 2018. Secure autonomous cyber-physical systems through verifiable information flow control. In Proc. Cyber-Physical Syst. Sec. Privacy (CPS-SPC). ACM, New York, NY, 48--59.

Digital Library

[91]

Juan Carlos Martínez Santos and Yunsi Fei. 2013. Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking. In Proc. Int. Workshop Hardw. Arch. Supp. Sec. Priv. (HASP). ACM, New York, NY, Article 6, 8 pages.

Digital Library

[92]

Juan Carlos Martinez Santos, Yunsi Fei, and Zhijie Jerry Shi. 2009. PIFT: Efficient dynamic information flow tracking using secure page allocation. In Proc. Workshop Embedd. Syst. Sec. (WESS). ACM, New York, NY, Article 6, 8 pages.

Digital Library

[93]

Juan Carlos Martinez Santos, Yunsi Fei, and Zhijie Jerry Shi. 2012. Static secure page allocation for light-weight dynamic information flow tracking. In Proc. Int. Conf. Compil. Archit. Synth. Embedded Syst. (CASES). ACM, New York, NY, 27--36.

Digital Library

[94]

Jamil Mazzawi and Ziyad Hanna. 2013. Formal analysis of security data paths in RTL design. In Hardware and Software: Verification and Testing, Armin Biere, Amir Nahir, and Tanja Vos (Eds.). Springer, Berlin, Germany, 7.

[95]

Mentor Graphics. 2015. From Simulation to Emulation—A Fully Reusable UVM Framework. Retrieved March 7, 2021 from https://www.mentor.com/products/fv/resources/overview/from-simulation-to-emulation-a-fully-reusable-uvm-framework-0def891c-ab7a-453d-b079-2c99f584650e.

[96]

MITRE. 2020. Common Weakness Enumeration (CWE). Retrieved March 7, 2021 from https://cwe.mitre.org/.

[97]

Tortuga Logic. 2019. Radix-M Hardware Security Platform for Firmware Security Validation. Retrieved March 7, 2021 from https://www.tortugalogic.com/radix-m/.

[98]

Tortuga Logic. 2019. Radix-S Hardware Root of Trust Security Verification Framework. Retrieved March 7, 2021 from https://www.tortugalogic.com/radix-s/.

[99]

Tortuga Logic. 2020. Measurable Hardware Security with MITRE CWEs. Retrieved March 7, 2021 from https://tortugalogic.com/tech-info/.

[100]

US Department of Defense. 1985. Department of Defense Trusted Computer System Evaluation Criteria. Palgrave Macmillan UK, London, UK.

[101]

John McLean. 1992. Proving noninterference and functional correctness using traces. J. Comp. Security 1, 1 (1992), 37--57.

Digital Library

[102]

Andreas Moser, Christopher Kruegel, and Engin Kirda. 2007. Exploring multiple execution paths for malware analysis. In Proc. IEEE Symp. Security Privacy (SP). IEEE, Los Alamitos, CA, 231--245.

Digital Library

[103]

Dejun Mu, Wei Hu, Baolei Mao, and Bo Ma. 2014. A bottom-up approach to verifiable embedded system information flow security. IET Inf. Sec. 8, 1 (Jan. 2014), 12--17.

[104]

Toby Murray, Daniel Matichuk, Matthew Brassil, Peter Gammie, Timothy Bourke, Sean Seefried, Corey Lewis, Xin Gao, and Gerwin Klein. 2013. seL4: From general purpose to a proof of information flow enforcement. In Proc. IEEE Symp. Security Privacy (SP). 415--429.

Digital Library

[105]

Andrew C. Myers and Barbara Liskov. 1997. A decentralized model for information flow control. ACM SIGOPS Oper. Syst. Rev. 31, 5 (1997), 129--142.

Digital Library

[106]

Vijay Nagarajan, Ho-Seop Kim, Youfeng Wu, and Rajiv Gupta. 2008. Dynamic information flow tracking on multicores. In Proc. Workshop Interac. Compil. Comp. Archit.

[107]

Adib Nahiyan, Jungmin Park, Miao He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor. 2020. SCRIPT: A CAD framework for power side-channel vulnerability assessment using information flow tracking and pattern generation. ACM Trans. Des. Autom. Electron. Syst. 25, 3 (May 2020), Article 26, 27 pages.

Digital Library

[108]

Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo Contreras, Domenic Forte, and Mark Tehranipoor. 2017. Hardware Trojan detection through information flow security verification. In Proc. IEEE Int. Test Conf. (ITC). 1--10.

[109]

James Newsome and Dawn Xiaodong Song. 2005. Dynamic taint analysis for automatic detection, analysis, and signature generation of exploits on commodity software. In Proc. Netw. Distrib. Syst. Sec. Symp. (NDSS), Vol. 5. 3--4.

[110]

Geraldine Shirley Nicholas, Yutian Gui, and Fareena Saqib. 2020. A survey and analysis on SoC platform security in ARM, Intel and RISC-V architecture. In Proc. IEEE Int. Midwest Symp. Circ. Syst. (MWSCAS). 718--721.

[111]

Edmund B. Nightingale, Daniel Peek, Peter M. Chen, and Jason Flinn. 2008. Parallelizing security checks on commodity hardware. In Proc. Int. Conf. Arch. Supp. Prog. Lang. Oper. Sys. (ASPLOS). ACM, New York, NY, 308--318.

Digital Library

[112]

Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. 2010. Theoretical analysis of gate level information flow tracking. In Proc. Des. Autom. Conf. (DAC). 244--247.

Digital Library

[113]

Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. 2011. Information flow isolation in I2C and USB. In Proc. Des. Autom. Conf. (DAC). ACM, New York, NY, 254--259.

Digital Library

[114]

Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, and Ryan Kastner. 2014. Leveraging gate-level properties to identify hardware timing channels. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 33, 9 (Sept. 2014), 1288--1301.

[115]

Jason Oberg, Timothy Sherwood, and Ryan Kastner. 2013. Eliminating timing information flows in a mix-trusted system-on-chip. IEEE Design Test 30, 2 (April 2013), 55--62.

[116]

Meltem Ozsoy, Dmitry Ponomarev, Nael Abu-Ghazaleh, and Tameesh Suri. 2014. SIFT: Low-complexity energy-efficient information flow tracking on SMT processors. IEEE Trans. Comput. 63, 2 (Feb. 2014), 484--496.

Digital Library

[117]

Christian Palmiero, Giuseppe Di Guglielmo, Luciano Lavagno, and Luca P. Carloni. 2018. Design and implementation of a dynamic information flow tracking architecture to secure a RISC-V core for IoT applications. In Proc. IEEE High Perform. Extreme Comput. Conf. (HPEC). 1--7.

[118]

Luca Piccolboni, Giuseppe Di Guglielmo, and Luca P. Carloni. 2018. PAGURUS: Low-overhead dynamic information flow tracking on loosely coupled accelerators. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 37, 11 (Nov. 2018), 2685--2696.

[119]

Pascal Pieper, Vladimir Herdt, Daniel Grobe, and Rolf Drechsler. 2020. Dynamic information flow tracking for embedded binaries using systemc-based virtual prototypes. In Proc. Des. Autom. Conf. (DAC). 1--6.

[120]

Christian Pilato, Kaijie Wu, Siddharth Garg, Ramesh Karri, and Francesco Regazzoni. 2019. TaintHLS: High-level synthesis for dynamic information flow tracking. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 38, 5 (May 2019), 798--808.

[121]

Joël Porquet and Simha Sethumadhavan. 2013. WHISK: An uncore architecture for dynamic information flow tracking in heterogeneous embedded SoCs. In Proc. Int. Conf. Hardware/Software Codesign Syst. Synth. (CODES+ISSS). IEEE, Los Alamitos, CA, Article 4, 9 pages.

[122]

SecVerilog Project. 2015. SecVerilog: Verilog + Information Flow V1.0. Retrieved March 7, 2021 from http://www.cs.cornell.edu/projects/secverilog/.

[123]

Maoyuan Qin, Wei Hu, Dejun Mu, and Yu Tai. 2018. Property based formal security varification for hardware Trojan detection. In Proc. IEEE Int. Verification Security Workshop (IVSW). IEEE, Los Alamitos, CA, 62--67.

[124]

Maoyuan Qin, Wei Hu, Xinmu Wang, Dejun Mu, and Baolei Mao. 2019. Theorem proof based gate level information flow tracking for hardware security verification. Computers Security 85 (2019), 225--239.

[125]

Sharon Rosenberg and Kathleen Meade. 2013. A Practical Guide to Adopting the Universal Verification Methodology (UVM). Cadence.

[126]

Olatunji Ruwase, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Shimin Chen, Michael Kozuch, and Michael Ryan. 2008. Parallelizing dynamic information flow tracking. In Proc. Symp. Parall. Algorithms Archit. (SPAA). ACM, New York, NY, 35--45.

Digital Library

[127]

Harry J. Saal and Israel Gat. 1978. A hardware architecture for controlling information flow. In Proc. Int. Symp. Comp. Archit. (ISCA). ACM, New York, NY, 73--77.

[128]

Andrei Sabelfeld and Andrew C. Myers. 2003. Language-based information-flow security. IEEE J. Sel. Areas Comm. 21, 1 (Jan. 2003), 5--19.

Digital Library

[129]

Hassan Salmani, Mohammad Tehranipoor, and Ramesh Karri. 2013. On design vulnerability analysis and trust benchmarks development. In Proc. IEEE Int. Conf. Comp. Des. (ICCD). 471--474.

[130]

Jerome H. Saltzer, David P. Reed, and David D. Clark. 1984. End-to-end arguments in system design. Technology 100 (1984), 0661.

[131]

Seaghan Sefton, Taiman Siddiqui, Nathaniel St. Amour, Gordon Stewart, and Avinash Karanth Kodi. 2018. GARUDA: Designing energy-efficient hardware monitors from high-level policies for secure information flow. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 37, 11 (Nov. 2018), 2509--2518.

[132]

Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby Lee, and Yunheung Paek. 2016. A hardware-based technique for efficient implicit information flow tracking. In Proc. Int. Conf. Comput.-Aided Des. (ICCAD). 1--7.

Digital Library

[133]

Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai. 2009. Low-overhead architecture for security tag. In Proc. IEEE Pacific Rim Int. Symp. Depend. Computing. 135--142.

Digital Library

[134]

Geraldine Shirley and Fareena Saqib. 2019. Information flow tracking in RISC-V. In Proc. IEEE Int. Conf. Smart Cities: Improving Quality of Life Using ICT IoT and AI (HONET-ICT). 199--200.

[135]

Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, and Fareena Saqib. 2019. Secure design flow of FPGA based RISC-V implementation. In Proc. IEEE Int. Verification Security Workshop (IVSW). 37--42.

[136]

Chengyu Song, Hyungon Moon, Monjur Alam, Insu Yun, Byoungyoung Lee, Taesoo Kim, Wenke Lee, and Yunheung Paek. 2016. HDFI: Hardware-assisted data-flow isolation. In Proc. IEEE Symp. Security Privacy (SP). 1--17.

[137]

Pramod Subramanyan and Divya Arora. 2014. Formal verification of taint-propagation security properties in a commercial SoC design. In Proc. Des. Autom. Test Europe Conf. Exhib. (DATE). IEEE, Los Alamitos, CA, Article 313, 2 pages.

[138]

Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, and Jason Fung. 2016. Verifying information flow properties of firmware using symbolic execution. In Proc. Des. Autom. Test Europe Conf. Exhib. (DATE). 337--342.

[139]

G. Edward Suh, Jae W. Lee, David Zhang, and Srinivas Devadas. 2004. Secure program execution via dynamic information flow tracking. In Proc. Int. Conf. Arch. Supp. Prog. Lang. Oper. Sys. (ASPLOS). ACM, New York, NY, 85--96.

Digital Library

[140]

Yu Tai, Wei Hu, Lantian Guo, Baolei Mao, and Dejun Mu. 2017. Gate level information flow analysis for multi-valued logic system. In Proc. Int. Conf. Image Vision Comput. (ICIVC). 1102--1106.

[141]

Yu Tai, Wei Hu, Dejun Mu, Baolei Mao, and Lu Zhang. 2018. Towards quantified data analysis of information flow tracking for secure system design. IEEE Access 6 (2018), 1822--1831.

[142]

Yu Tai, Wei Hu, Lu Zhang, Dejun Mu, and Ryan Kastner. 2021. A multi-flow information flow tracking approach for proving quantitative hardware security properties. Tsinghua Sci. Tech. 26, 1 (2021), 62--71.

[143]

Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederic T. Chong, and Timothy Sherwood. 2009. Execution leases: A hardware-supported mechanism for enforcing strong non-interference. In Proc. Int. Symp. Microarchitecture (MICRO). 493--504.

Digital Library

[144]

Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, and Timothy Sherwood. 2010. Gate-level information-flow tracking for secure architectures. IEEE Micro 30, 1 (Jan. 2010), 92--100.

Digital Library

[145]

Mohit Tiwari, Jason K. Oberg, Xun Li, Jonathan Valamehr, Timothy Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, and Timothy Sherwood. 2011. Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security. In Proc. Int. Symp. Comp. Archit. (ISCA). 189--199.

Digital Library

[146]

Mohit Tiwari, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, and Timothy Sherwood. 2009. Complete information flow tracking from the gates up. In Proc. Int. Conf. Arch. Supp. Prog. Lang. Oper. Sys. (ASPLOS). 109--120.

Digital Library

[147]

Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev, Nael Abu-Ghazaleh, and Lei Yu. 2019. LATCH: A locality-aware taint checker. In Proc. Int. Symp. Microarchitecture (MICRO). ACM, New York, NY, 969--982.

Digital Library

[148]

Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, and David I. August. 2004. RIFLE: An architectural framework for user-centric information-flow security. In Proc. Int. Symp. Microarchitecture (MICRO). 243--254.

[149]

Guru Venkataramani, Ioannis Doudalis, Yan Solihin, and Milos Prvulovic. 2008. FlexiTaint: A programmable accelerator for dynamic taint propagation. In Proc. IEEE Int. Symp. High Perform. Comp. Archit. (HPCA). 173--184.

[150]

Dennis Volpano, Cynthia Irvine, and Geoffrey Smith. 1996. A sound type system for secure flow analysis. J. Comp. Security 4, 2-3 (1996), 167--187.

[151]

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapotre, and Guy Gogniat. 2018. A small and adaptive coprocessor for information flow tracking in ARM SoCs. In Proc. Int. Conf. Reconfig. Comput. FPGAs (ReConFig). 1--8.

[152]

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, and Guy Gogniat. 2016. Towards a hardware-assisted information flow tracking ecosystem for ARM processors. In Proc. Int. Conf. Field Programm. Logic App. (FPL). 1--2.

[153]

Muhammad A. Wahab, Pascal Cotret, Mounir N. Allah, Guillaume Hiet, Vianney Lapôtre, and Guy Gogniat. 2017. ARMHEx: A hardware extension for DIFT on ARM-based SoCs. In Proc. Int. Conf. Field Programm. Logic App. (FPL). 1--7.

[154]

Chenguang Wang, Yici Cai, and Qiang Zhou. 2018. HLIFT: A high-level information flow tracking method for detecting hardware Trojans. In Proc. Asia South Pacific Des. Autom. Conf. (ASP-DAC). 727--732.

[155]

Ofir Weisse, Jo Van Bulck, Marina Minkin, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Raoul Strackx, Thomas F. Wenisch, and Yuval Yarom. 2018. Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution. Retrieved March 7, 2021 from https://foreshadowattack.eu/foreshadow-NG.pdf.

[156]

William Wulf, Ellis Cohen, William Corwin, Anita Jones, Roy Levin, Charles Pierson, and Fred Pollack. 1974. Hydra: The kernel of a multiprocessor operating system. Commun. ACM 17, 6 (1974), 337--345.

Digital Library

[157]

Kaiyuan Yang, Matthew Hicks, Qing Dong, Todd Austin, and Dennis Sylvester. 2016. A2: Analog malicious hardware. In Proc. IEEE Symp. Security Privacy (SP). 18--37.

[158]

Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher W. Fletcher. 2019. Speculative taint tracking (STT): A comprehensive protection for speculatively accessed data. In Proc. Int. Symp. Microarchitecture (MICRO). ACM, New York, NY, 954--968.

[159]

Young-Nam Yun, Jae-Beom Kim, Nam-Do Kim, and Byeong Min. 2011. Beyond UVM for practical SoC verification. In Proc. Int. SoC Des. Conf. (ISOCC). 158--162.

[160]

Drew Zagieboylo, G. Edward Suh, and Andrew C. Myers. 2019. Using information flow to design an ISA that controls timing channels. In Proc. IEEE Comp. Sec. Foundations Symp. (CSF). 272--27215.

[161]

Nickolai Zeldovich, Silas Boyd-Wickizer, Eddie Kohler, and David Mazières. 2011. Making information flow explicit in HiStar. Commun. ACM 54, 11 (2011), 93--101.

Digital Library

[162]

Nickolai Zeldovich, Silas Boyd-Wickizer, and David Mazieres. 2008. Securing distributed systems with information flow control. In Proc. Netw. Syst. Des. Impl. (NSDI), Vol. 8. 293--308.

[163]

Danfeng Zhang, Yao Wang, G. Edward Suh, and Andrew C. Myers. 2015. A hardware design language for timing-sensitive information-flow security. In Proc. Int. Conf. Arch. Supp. Prog. Lang. Oper. Sys. (ASPLOS). ACM, New York, NY, 503--516.

[164]

Rui Zhang and Cynthia Sturton. 2020. Transys: Leveraging common security properties across hardware designs. In Proc. IEEE Symp. Security Privacy (SP). 1713--1727.

[165]

Hu Zhaohui, Arnaud Pierres, Hu Shiqing, Chen Fang, Philippe Royannez, Eng Pek See, and Yean Ling Hoon. 2012. Practical and efficient SOC verification flow by reusing IP testcase and testbench. In Proc. Int. SoC Des. Conf. (ISOCC). IEEE, Los Alamitos, CA, 175--178.

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Index Terms

Hardware Information Flow Tracking
1. General and reference
  1. Document types
    1. Surveys and overviews
2. Security and privacy
  1. Formal methods and theory of security
    1. Formal security models
    2. Logic and verification
  2. Systems security
    1. Information flow control

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 54, Issue 4

May 2022

782 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/3464463

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Revised: 01 January 2021

Received: 01 April 2020

Published in CSUR Volume 54, Issue 4

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Palanisamy Sundar ALi FZou XGao T(2024)Subjective Logic-based Decentralized Federated Learning for Non-IID DataProceedings of the 19th International Conference on Availability, Reliability and Security10.1145/3664476.3664517(1-11)Online publication date: 30-Jul-2024
https://dl.acm.org/doi/10.1145/3664476.3664517
Saha SImtiaz H(2024)Privacy-Preserving Non-Negative Matrix Factorization with OutliersACM Transactions on Knowledge Discovery from Data10.1145/363296118:3(1-26)Online publication date: 12-Jan-2024
https://dl.acm.org/doi/10.1145/3632961
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Reimann LPrashar AGhinami CPelke RSisejkovic DMerchant FLeupers R(2024)QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)10.1109/VLSITSA60681.2024.10546389(1-4)Online publication date: 22-Apr-2024
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