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Toward nanometric scale integration: an automatic routing approach for NML circuits

Published: 26 August 2019 Publication History

Abstract

In recent years, many technologies have been studied to replace or complement CMOS. Some of these emerging technologies are known as Field Coupled Nanocomputing. However, these new technologies introduce the need for developing tools to perform circuit mapping, placement, and routing. Nanomagnetic Logic Circuit (NML) is one of these emergent technologies. It relies on the magnetization of nanomagnets to perform operations through majority logic. In this work, we propose an approach to map a gate-level circuit to an NML layout automatically. We use the Breadth First Search to perform the placement and the A* algorithm to transverse the circuit and build the routes for each node. To evaluate the effectiveness of our approach, we use a series of ISCAS'85 benchmarks. Our results show an area reduction varying from 20% to 60%.

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  • (2022)An automatic routing approach for NML circuitsJournal of Computational Electronics10.1007/s10825-022-01960-3Online publication date: 7-Nov-2022
  1. Toward nanometric scale integration: an automatic routing approach for NML circuits

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    cover image ACM Conferences
    SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design
    August 2019
    204 pages
    ISBN:9781450368445
    DOI:10.1145/3338852
    © 2019 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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    Published: 26 August 2019

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    Author Tags

    1. NML
    2. nanocomputing
    3. routing

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    • (2022)An automatic routing approach for NML circuitsJournal of Computational Electronics10.1007/s10825-022-01960-3Online publication date: 7-Nov-2022

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