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The Arm Triple Core Lock-Step (TCLS) Processor

Published: 17 June 2019 Publication History

Abstract

The Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and availability in safety-critical and ultra-reliable applications. TCLS is simple, scalable, and easy to deploy in applications where Arm DCLS processors are widely used (e.g., automotive), as well as in new sectors where the presence of Arm technology is incipient (e.g., enterprise) or almost non-existent (e.g., space). Specifically in space, COTS Arm processors provide optimal power-to-performance, extensibility, evolvability, software availability, and ease of use, especially in comparison with the decades old rad-hard computing solutions that are still in use. This article discusses the fundamentals of an Arm Cortex-R5 based TCLS processor, providing key functioning and implementation details. The article shows that the TCLS architecture keeps the use of rad-hard technology to a minimum, namely, using rad-hard by design standard cell libraries only to protect the critical parts that account for less than 4% of the entire TCLS solution. Moreover, when exposure to radiation is relatively low, such as in terrestrial applications or even satellites operating in Low Earth Orbits (LEO), the system could be implemented entirely using commercial cell libraries, relying on the radiation mitigation methods implemented on the TCLS to cope with sporadic soft errors in its critical parts. The TCLS solution allows thus to significantly reduce chip manufacturing costs and keep pace with advances in low power consumption and high density integration by leveraging commercial semiconductor processes, while matching the reliability levels and improving availability that can be achieved using extremely expensive rad-hard semiconductor processes. Finally, the article describes a TRL4 proof-of-concept TCLS-based System-on-Chip (SoC) that has been prototyped and tested to power the computer on-board an Airbus Defence and Space telecom satellite. When compared to the currently used processor solution by Airbus, the TCLS-based SoC results in a more than 5× performance increase and cuts power consumption by more than half.

References

[1]
Aeroflex Gaisler. 2015. UT700 32-bit Fault-Tolerant SPARC V8/LEON 3FT Processor. Technical Report.
[2]
T. Amort, W. Snapp, J. Evans, J. Popp, M. Cabanas-Holmen, and E. Cannon. 2011. 90nm RHBD ASIC design capability. In Proceedings of the Military and Aerospace Programmable Logic Devices Workshop.
[3]
G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Floria, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys. 1999. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects. IEEE Transactions on Nuclear Science 46, 6 (1999), 1690--1696.
[4]
Arm Ltd. 2011. Cortex-R5 and Cortex-R5F. Technical Reference Manual. Technical Report.
[5]
Atmel Corp. 2004. Rad-Hard 32-bit SPARC Embedded Processor TSC695F. Technical Report.
[6]
Atmel Corp. 2005. ATC18RHA Rad-Hard 0.18m CMOS Cell-Based ASIC Family for Space Use. Technical Report.
[7]
Atmel Corp. 2011. Rad-Hard 32-bit SPARC V8 Processor AT697F. Technical Report.
[8]
Atmel Corp. 2016. Space components vs parts for automotive applications. In Proceedings of the European Space Components Conference.
[9]
A. Avizienis, J. C. Laprie, B. Randell, and C. Landwehr. 2004. Basic concepts and taxonomy of dependable and secure computing. IEEE Transactions on Dependable and Secure Computing 1, 1 (2004), 11--33.
[10]
BAE Systems. 2008. RAD750 Radiation-Hardened PowerPC Microprocessor. Technical Report.
[11]
BAE Systems. 2017. RAD5545 Multi-Core System-on-Chip Power Architecture Processor. Technical Report.
[12]
M. Berg. 2013. Revisiting dual interlocked storage cell (DICE) single event upset (SEU) sensitivity. In Proceedings of the Microelectronics Reliability and Qualification Working Meeting.
[13]
T. Calin, M. Nicolaidis, and R. Velazco. 1996. Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science 43, 6 (1996), 2874--2878.
[14]
Cobham. 2016. GR712RC Data Sheet. Technical Report.
[15]
W. R. Dawes, G. F. Derbenwick, and B. L. Gregory.1976. Process technology for radiation-hardened CMOS integrated circuits. IEEE Journal of Solid-State Circuits 11, 4 (1976), 459--465.
[16]
R. DeCoursey, R. Melton, and R. R. Estes. 2006. Non-radiation hardened microprocessors in space-based remote sensing systems. In Proceedings of the SPIE Europe Remote Sensing Conference.
[17]
V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, and M. J. Irwin. 2006. Effect of Power Optimizations on Soft Error Rate. Springer, Chapter 1, 1--20.
[18]
R. Doyle, R. Some, W. Powell, G. Mounce, M. Goforth, S. Horan, and M. Lowry. 2014. High performance spaceflight computing (HPSC) next-generation space processor (NGSP): A joint investment of NASA and AFRL. In Proceedings of the International Symposium on Artificial Intelligence, Robotics, and Automation in Space.
[19]
ESA/ESTEC. 2018a. Statement of Work: Arm-based MCU (TEC/2016.43). Retrieved March 6, 2018 from http://emits.sso.esa.int/emits/owa/emits_online.showao?typ1=75938user=Anonymous.
[20]
ESA/ESTEC. 2018b. This is the Year Internet from Space gets Really Serious. Retrieved January 7, 2019 from http://www.universetoday.com/138210/year-internet-space-gets-really-serious.
[21]
M. M. Ghahroodi, E. Ozer, and D. Bull. 2013. SEU and SET-tolerant Arm Cortex-R4 CPU for space and avionics applications. In Proceedings of the Workshop on Manufacturable and Dependable Multi-core Architectures at Nanoscale.
[22]
R. Ginosar. 2012. Survey of processors for space. In Proceedings of the Data Systems in Aerospace Conference.
[23]
D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S. Siva, S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. 2011. Architectures for online error detection and recovery in multicore processors. In Proceedings of the Conference on Design, Automation and Test in Europe.
[24]
GomSpace A/S. 2017. NanoMind Z7000 Datasheet On-board CPU and FPGA for Space Applications. Technical Report.
[25]
L. Hansen. 2016. Unleash the Unparalleled Power and Flexibility of Zynq UltraScale+ MPSoCs - WP470.
[26]
M. J. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, and W. Craig. 1998. Latchup in CMOS technology. In Proceedings of the IEEE International Reliability Physics Symposium.
[27]
R. Hillman, G. Swift, P. Layton, M. Conrad, C. Thibodeau, and F. Irom. 2003. Space processor radiation mitigation and validation techniques for an 1,800 MIPS processor board. In Proceedings of the European Conference on Radiation and Its Effects on Components and Systems.
[28]
M. Hjorth, M. Aberg, N. J. Wessman, J. Andersson, R. Chevallier, R. Forsyth, R. Weigand, and L. Fossati. 2015. GR740: Rad-hard quad-core LEON4FT system-on-chip. In Proceedings of the Data Systems in Aerospace Conference.
[29]
Infineon Tech. 2012. Tricore: Highly Integrated and Performance Optimized 32-bit Microcontrollers for Automotive and Industrial Applications. Technical Report.
[30]
X. Iturbe, D. Keymeulen, P. Yiu, D. Berisford, R. Carlson, K. Hand, and E. Ozer. 2016a. On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration. Springer, Chapter 1, 1--22.
[31]
X. Iturbe, B. Venu, J. Jagst, E. Ozer, P. Harrod, C. Turner, and J. Penton. 2018. Addressing functional safety challenges in autonomous vehicles with the arm triple core lock-step (TCLS) architecture. IEEE Design and Test Magazine 35, 3 (2018), 7--14.
[32]
X. Iturbe, B. Venu, and E. Ozer. 2016b. Soft error vulnerability assessment of the real-time safety-related Arm Cortex-R5 CPU. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
[33]
X. Iturbe, B. Venu, E. Ozer, and S. Das. 2016c. A triple core lock-step (TCLS) Arm Cortex-R5 processor for safety-critical and ultra-reliable applications. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks.
[34]
C. M. Jeffery and R. J. O. Figueiredo. 2012. A flexible approach to improving system reliability with virtual lockstep. IEEE Transactions on Dependable and Secure Computing 9, 1 (2012), 2--15.
[35]
A. H. Johnston. 2000. Scaling and technology issues for soft error rates. In Proceedings of the Annual Research Conference on Reliability.
[36]
M. Kaliorakis, D. Gizopoulos, R. Canal, and A. Gonzalez. 2017. MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment. In Proceedings of the 2017 Annual International Symposium on Computer Architecture.
[37]
S. Kanekal, A. Jones, B. Randol, D. Patel, E. Summerlin, E. Gorman, G. Crum, G. D. Nolfo, N. Paschalidis, S. Heyward, and S. Riall. 2014. CeREs: A compact radiation belt explorer. In Proceedings of the AIAA/USU Conference on Small Satellites.
[38]
F. Koebel and J. F. Coldefy. 2010. SCOC3: A space computer on a chip. In Proceedings of the Conference on Design, Automation and Test in Europe.
[39]
P. Koopman and M. Wagner. 2016. Challenges in autonomous vehicle testing and validation. In Proceedings of the SAE World Congress Conference.
[40]
T. Kuschel, R. Mariani, and H. Shigehara. 2010. A flexible microcontroller architecture for fail-safe and fail-operational systems. In Proceedings of the HiPEAC Workshop on Design for Reliability.
[41]
R. C. Lacoe, J. V. Osborn, R. Koga, S. Brown, and D.C. Mayer. 2000. Application of hardness-by-design methodology to radiation-tolerant ASIC technologies. IEEE Transactions on Nuclear Science 47, 6 (2000), 2334--2341.
[42]
M. D. Lam, E. E. Rothberg, and M. E. Wolf. 1991. The cache performance and optimizations of blocked algorithms. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems.
[43]
S. Lin, Y. B. Kim, and F. Lombardi. 2011. A 11-transistor nanoscale CMOS memory cell for hardening to soft errors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 5 (2011), 900--904.
[44]
Lockheed Martin. 1995. RAD6000 Radiation Hardened 32-Bit Processor. Technical Report.
[45]
Maxwell Tech. 2013. SCS750 Single Board Computer for Space. Technical Report.
[46]
Moog Broad Reach. 2015. BRE440 Rad-Hard CPU. Technical Report.
[47]
NASA. 2015. Statement of Work (SOW) for the Development of the High Performance Space Computing (HPSC) Processor. Technical Report.
[48]
E. Normand. 1996. Single event upset at ground level. IEEE Transactions on Nuclear Science 43, 6 (1996), 2742--2750.
[49]
E. Normand. 2000. Radiation Effects in Spacecraft and Aircraft. Retrieved January 7, 2019 from http://lws.gsfc.nasa.gov/documents/mission_requirements/normand_020900.pdf.
[50]
NXP. 2012. Automotive Solutions Setting the Pace for Innovation. Technical Report.
[51]
M. Pignol. 2010. COTS-based applications in space avionics. In Proceedings of the Conference on Design, Automation and Test in Europe.
[52]
J. L. Poupat. 2017. DAHLIA system-on-chip. In Proceedings of the IEEE International Conference on Space Mission Challenges for Information Technology.
[53]
J. L. Poupat, B. Leroy, and T. Helfers. 2017. TCLS arm for space. In Proceedings of the Conference on Data Systems in Aerospace.
[54]
Renesas. 2015. Main Specifications of the R-Car H3 SoC. Technical Report.
[55]
S. Resch, A. Steininger, and C. Scherrer. 2013. Software composability and mixed criticality for triple modular redundant architectures. In Proceedings of the SASSUR International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems.
[56]
J. Rhea. 2002. BAE Systems moves into Third Generation Rad-Hard Processors. Retrieved January 7, 2019 from http://www.militaryaerospace.com/articles/print/volume-13/issue-5/news/bae-systems-moves-into-third-generation-rad-hard-processors.html.
[57]
T. Romanko and B. Clegg. 2005. SOI Eases Radiation-Hardened ASIC Designs. Retrieved January 7, 2019 from https://www.design-reuse.com/articles/10962/soi-eases-radiation-hardened-asic-designs.html.
[58]
D. Rudolph, C. Wilson, J. Stewart, P. Gauvin, A. George, H. Lam, G. Crum, M. Wirthlin, A. Wilson, and A. Stoddard. 2014. CHREC space processor: A multifaceted hybrid architecture for space computing. In Proceedings of the AIAA/USU Conference on Small Satellites.
[59]
H. Saito, Y. Masumoto, T. Mizuno, A. Miura, M. Hashimoto, H. Ogawa, S. Tachikawa, T. Oshima, A. Choki, H. Fukuda, M. Hirahara, and S. Okano. 2001. Piggy-back satellite for Aurora observation and technology demonstration. Acta Astronautica 48, 5 (2001), 723--735.
[60]
K. M. Schlesier. 1974. Radiation hardening of CMOS/SOS integrated circuits. IEEE Transactions on Nuclear Science 47, 6 (1974), 152--158.
[61]
T. Scholastique and L. Hili. 2017. A 65nm Hardened ASIC Technology for Space Applications. Retrieved January 7, 2019 from http://indico.esa.int/indico/event/165/contribution/13/material/1/1.pdf.
[62]
M. R. Shaneyfelt, P. E. Dodd, B. L. Draper, and R. S. Flores. 1998. Challenges in hardening technologies using shallow-trench isolation. IEEE Transactions on Nuclear Science 45, 6 (1998), 2584--2592.
[63]
Texas Instruments. 2014. Hercules TMS570 Microcontrollers. Technical Report.
[64]
B. Venu, E. Ozer, X. Iturbe, and A. Robinson. 2016. A fail-functional automotive CPU subsystem architecture for mitigating single point of failures. In Proceedings of the IEEE International Workshop on Automotive Reliability and Test.
[65]
A. Vernile. 2018. The Rise of Private Actors in the Space Sector. Springer.
[66]
Vorago Tech. 2017. VA10820 - Radiation Hardened Arm Cortex-M0 MCU Datasheet. Technical Report.
[67]
R. Whitwam. 2014. NASA’s Orion Spacecraft runs on a 12 Year-old Single-Core Processor from the iBook G3. Retrieved January 7, 2019 from https://www.geek.com/chips/nasas-orion-spacecraft-runs-on-a-12-year-old-single-core-processor-from-the-ibook-g3-1611132/.
[68]
C. Wilson, J. Stewart, P. Gauvin, J. MacKinnon, J. Coole, J. Urriste, A. George, G. Crum, E. Timmons, J. Beck, T. Flatley, A. Wilson, M. Wirthlin, and A. Stoddard. 2014. CSP hybrid space computing for STP-H5/ISEM on ISS. In Proceedings of the AIAA/USU Conference on Small Satellites.

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Published In

cover image ACM Transactions on Computer Systems
ACM Transactions on Computer Systems  Volume 36, Issue 3
August 2018
99 pages
ISSN:0734-2071
EISSN:1557-7333
DOI:10.1145/3341160
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Accepted: 01 November 2019
Published: 17 June 2019
Revised: 01 June 2018
Received: 01 October 2017
Published in TOCS Volume 36, Issue 3

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Author Tags

  1. Arm
  2. safety-critical
  3. soft error resilience
  4. space avionics

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  • Research-article
  • Research
  • Refereed

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  • European Union's Horizon 2020 research and innovation program
  • European Union's FP7 Marie-Curie international outgoing fellowship program

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