research-article

Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors

Authors:

Vedad Hadžić,

Michael Schwarz,

Clémentine Maurice,

Daniel GrussAuthors Info & Claims

ASIA CCS '20: Proceedings of the 15th ACM Asia Conference on Computer and Communications Security

Pages 813 - 825

https://doi.org/10.1145/3320269.3384746

Published: 05 October 2020 Publication History

Abstract

To optimize the energy consumption and performance of their CPUs, AMD introduced a way predictor for the L1-data (L1D) cache to predict in which cache way a certain address is located. Consequently, only this way is accessed, significantly reducing the power consumption of the processor. In this paper, we are the first to exploit the cache way predictor. We reverse-engineered AMD's L1D cache way predictor in microarchitectures from 2011 to 2019, resulting in two new attack techniques. With Collide+Probe, an attacker can monitor a victim?s memory accesses without knowledge of physical addresses or shared memory when time-sharing a logical core. With Load+Reload, we exploit the way predictor to obtain highly-accurate memory-access traces of victims on the same physical core. While Load+Reload relies on shared memory, it does not invalidate the cache line, allowing stealthier attacks that do not induce any last-level-cache evictions. We evaluate our new side channel in different attack scenarios. We demonstrate a covert channel with up to 588.9 kB/s, which we also use in a Spectre attack to exfiltrate secret data from the kernel. Furthermore, we present a key-recovery attack from a vulnerable cryptographic implementation. We also show an entropy-reducing attack on ASLR of the kernel of a fully patched Linux system, the hypervisor, and our own address space from JavaScript. Finally, we propose countermeasures in software and hardware mitigating the presented attacks

References

[1]

Andreas Abel and Jan Reineke. 2013. Measurement-based Modeling of the Cache Replacement Policy. In Real-Time and Embedded Technology and Applications Symposium (RTAS) .

[2]

Advanced Micro Devices Inc. 2013. BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors.

[3]

Advanced Micro Devices Inc. 2014. Software Optimization Guide for AMD Family 15h Processors.

[4]

Advanced Micro Devices Inc. 2017a. AMD64 Architecture Programmer's Manual .

[5]

Advanced Micro Devices Inc. 2017b. Software Optimization Guide for AMD Family 17h Processors .

[6]

Advanced Micro Devices Inc. 2018. Software Techniques for Managing Speculation on AMD Processors . Revison 7.10.18.

[7]

Advanced Micro Devices Inc. 2019. 2nd Gen AMD EPYC Processors Set New Standard for the Modern Datacenter with Record-Breaking Performance and Significant TCO Savings.

[8]

Alejandro Cabrera Aldaya, Billy Bob Brumley, Sohaib ul Hassan, Cesar Pereida Garcí a, and Nicola Tuveri. 2018. Port Contention for Fun and Profit. In S&P.

[9]

Alex Christensen. 2015. Reduce resolution of performance.now. https://bugs.webkit.org/show_bug.cgi?id=146531

[10]

Ricardo Alves, Stefanos Kaxiras, and David Black-Schaffer. 2018. Dynamically disabling way-prediction to reduce instruction replay. In International Conference on Computer Design (ICCD) .

[11]

Antonio Barresi, Kaveh Razavi, Mathias Payer, and Thomas R. Gross. 2015. CAIN: Silently Breaking ASLR in the Cloud. In WOOT.

[12]

Daniel J. Bernstein. 2005. Cache-Timing Attacks on AES . http://cr.yp.to/antiforgery/cachetiming-20050414.pdf

[13]

Atri Bhattacharyya, Alexandra Sandulescu, Matthias Neugschwandt ner, Alessandro Sorniotti, Babak Falsafi, Mathias Payer, and Anil Kurmus. 2019. SMoTherSpectre: exploiting speculative execution through port contention. In CCS .

[14]

Boris Zbarsky. 2015. Reduce resolution of performance.now. https://hg.mozilla.org/integration/mozilla-inbound/rev/48ae8b5e62ab

[15]

Claudio Canella, Daniel Genkin, Lukas Giner, Daniel Gruss, Moritz Lipp, Marina Minkin, Daniel Moghimi, Frank Piessens, Michael Schwarz, Berk Sunar, Jo Van Bulck, and Yuval Yarom. 2019 a. Fallout: Leaking Data on Meltdown-resistant CPUs. In CCS .

[16]

Claudio Canella, Jo Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019 b. A Systematic Evaluation of Transient Execution Attacks and Defenses. In USENIX Security Symposium . Extended classification tree and PoCs at https://transient.fail/.

[17]

Mike Clark. 2016. A new x86 core architecture for the next generation of computing. In IEEE Hot Chips Symposium (HCS) .

[18]

Stephen Crane, Andrei Homescu, Stefan Brunthaler, Per Larsen, and Michael Franz. 2015. Thwarting Cache Side-Channel Attacks Through Dynamic Software Diversity. In NDSS .

[19]

Joan Daemen and Vincent Rijmen. 2013. The design of Rijndael: AES-the advanced encryption standard .

[20]

Helder Eijs. 2018. PyCryptodome: A self-contained cryptographic library for Python . https://www.pycryptodome.org

[21]

Dmitry Evtyushkin, Dmitry Ponomarev, and Nael Abu-Ghazaleh. 2016. Jump over ASLR: Attacking branch predictors to bypass ASLR. In MICRO .

[22]

W. Shen Gene and S. Craig Nelson. 2006. MicroTLB and micro tag for reducing power in a processor . US Patent 7,117,290 B2.

[23]

Ben Gras, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2018. Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks. In USENIX Security Symposium .

[24]

Ben Gras, Kaveh Razavi, Erik Bosman, Herbert Bos, and Cristiano Giuffrida. 2017. ASLR on the Line: Practical Cache Attacks on the MMU. In NDSS.

[25]

Leon Groot Bruinderink, Andreas Hülsing, Tanja Lange, and Yuval Yarom. 2016. Flush, Gauss, and Reload -- A Cache Attack on the BLISS Lattice-Based Signature Scheme. In CHES .

[26]

William Gropp, Ewing Lusk, Nathan Doss, and Anthony Skjellum. 1996. A high-performance, portable implementation of the MPI message passing interface standard. Parallel computing (1996).

[27]

Daniel Gruss, Moritz Lipp, Michael Schwarz, Richard Fellner, Clémentine Maurice, and Stefan Mangard. 2017. KASLR is Dead: Long Live KASLR. In ESSoS.

[28]

Daniel Gruss, Clémentine Maurice, Anders Fogh, Moritz Lipp, and Stefan Mangard. 2016b. Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR. In CCS .

[29]

Daniel Gruss, Clémentine Maurice, and Stefan Mangard. 2016a. Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript. In DIMVA .

[30]

Daniel Gruss, Clémentine Maurice, Klaus Wagner, and Stefan Mangard. 2016c. Flush

[31]

Flush: A Fast and Stealthy Cache Attack . In DIMVA .

[32]

Daniel Gruss, Raphael Spreitzer, and Stefan Mangard. 2015. Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches. In USENIX Security Symposium .

[33]

Shay Gueron. 2012. Intel Advanced Encryption Standard (Intel AES) Instructions Set -- Rev 3.01 .

[34]

Richard W Hamming. 1950. Error detecting and error correcting codes. The Bell system technical journal (1950).

[35]

Joel Hruska. 2019. AMD Gains Market Share in Desktop and Laptop, Slips in Servers . https://www.extremetech.com/computing/291032-amd

[36]

Ralf Hund, Carsten Willems, and Thorsten Holz. 2013. Practical Timing Side Channel Attacks against Kernel Space ASLR. In S&P.

[37]

Koji Inoue, Tohru Ishihara, and Kazuaki Murakami. 1999. Way-predicting set-associative cache for high performance and low energy consumption. In Symposium on Low Power Electronics and Design .

Digital Library

[38]

Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar. 2015. S$A: A Shared Cache Attack that Works Across Cores and Defies VM Sandboxing -- and its Application to AES. In S&P .

[39]

Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar. 2016. Cross processor cache attacks. In AsiaCCS .

[40]

Yeongjin Jang, Sangho Lee, and Taesoo Kim. 2016. Breaking Kernel Address Space Layout Randomization with Intel TSX. In CCS .

[41]

Richard E Kessler. 1999. The alpha 21264 microprocessor. IEEE Micro (1999).

Digital Library

[42]

Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre Attacks: Exploiting Speculative Execution. In S&P .

[43]

Paul C. Kocher. 1996. Timing Attacks on Implementations of Diffe-Hellman, RSA, DSS, and Other Systems. In CRYPTO .

[44]

Robert Könighofer. 2008. A Fast and Cache-Timing Resistant Implementation of the AES. In CT-RSA .

[45]

Esmaeil Mohammadian Koruyeh, Khaled Khasawneh, Chengyu Song, and Nael Abu-Ghazaleh. 2018. Spectre Returns! Speculation Attacks using the Return Stack Buffer. In WOOT.

[46]

Marcin Krzyzanowski. 2019. CryptoSwift: Growing collection of standard and secure cryptographic algorithms implemented in Swift . https://cryptoswift.io

[47]

Linux. 2019 a. Complete virtual memory map with 4-level page tables. https://www.kernel.org/doc/Documentation/x86/x86_64/mm.txt

[48]

Linux. 2019 b. Linux Kernel 5.0 Process (x86) . https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/kernel/process.c

[49]

Moritz Lipp, Daniel Gruss, Raphael Spreitzer, Clémentine Maurice, and Stefan Mangard. 2016. ARMageddon: Cache Attacks on Mobile Devices. In USENIX Security Symposium .

[50]

Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading Kernel Memory from User Space . In USENIX Security Symposium .

[51]

Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, and Ruby B. Lee. 2015. Last-Level Cache Side-Channel Attacks are Practical. In S&P .

[52]

G. Maisuradze and C. Rossow. 2018. ret2spec: Speculative Execution Using Return Stack Buffers. In CCS .

[53]

Clémentine Maurice, Nicolas Le Scouarnec, Christoph Neumann, Olivier Heen, and Aurélien Francillon. 2015. Reverse Engineering Intel Complex Addressing Using Performance Counters. In RAID.

[54]

Clémentine Maurice, Manuel Weber, Michael Schwarz, Lukas Giner, Daniel Gruss, Carlo Alberto Boano, Stefan Mangard, and Kay Römer. 2017. Hello from the Other Side: SSH over Robust Cache Covert Channels in the Cloud. In NDSS .

[55]

Ahmad Moghimi, Gorka Irazoqui, and Thomas Eisenbarth. 2017. Cachezoom: How SGX amplifies the power of cache attacks. In CHES.

[56]

Richard Moore. 2017. pyaes: Pure-Python implementation of AES block-cipher and common modes of operation . https://github.com/ricmoo/pyaes

[57]

Louis-Marie Vincent Mouton, Nicolas Jean Phillippe Huot, Gilles Eric Grandou, and Stephane Eric Sebastian Brochier. 2012. Cache accessing using a micro TAG. US Patent 8,151,055.

[58]

Yossef Oren, Vasileios P Kemerlis, Simha Sethumadhavan, and Angelos D Keromytis. 2015. The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications. In CCS .

[59]

Dag Arne Osvik, Adi Shamir, and Eran Tromer. 2006. Cache Attacks and Countermeasures: the Case of AES. In CT-RSA .

[60]

Colin Percival. 2005. Cache missing for fun and profit. In BSDCan .

[61]

Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, and Stefan Mangard. 2016. DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks. In USENIX Security Symposium .

[62]

Moinuddin K Qureshi. 2019. New attacks and defense for encrypted-address cache. In ISCA .

[63]

Chester Rebeiro, A. David Selvakumar, and A. S. L. Devi. 2006. Bitslice Implementation of AES. In Cryptology and Network Security (CANS).

[64]

David J Sager and Glenn J Hinton. 2002. Way-predicting cache memory. US Patent 6,425,055.

[65]

Michael Schwarz, Claudio Canella, Lukas Giner, and Daniel Gruss. 2019 a. Store-to-Leak Forwarding: Leaking Data on Meltdown-resistant CPUs . arXiv:1905.05725 (2019).

[66]

Michael Schwarz, Daniel Gruss, Samuel Weiser, Clémentine Maurice, and Stefan Mangard. 2017a. Malware Guard Extension: Using SGX to Conceal Cache Attacks. In DIMVA .

[67]

Michael Schwarz, Moritz Lipp, Daniel Gruss, Samuel Weiser, Clémentine Maurice, Raphael Spreitzer, and Stefan Mangard. 2018. KeyDrown: Eliminating Software-Based Keystroke Timing Side-Channel Attacks. In NDSS .

[68]

Michael Schwarz, Moritz Lipp, Daniel Moghimi, Jo Van Bulck, Julian Stecklina, Thomas Prescher, and Daniel Gruss. 2019 b. ZombieLoad: Cross-Privilege-Boundary Data Sampling. In CCS .

[69]

Michael Schwarz, Clémentine Maurice, Daniel Gruss, and Stefan Mangard. 2017b. Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript. In FC .

[70]

Michael Schwarz, Martin Schwarzl, Moritz Lipp, and Daniel Gruss. 2019 c. NetSpectre: Read Arbitrary Memory over Network . In ESORICS .

[71]

Mark Seaborn. 2015. How physical addresses map to rows and banks in DRAM . http://lackingrhoticity.blogspot.com/2015/05/how-physical-addresses-map-to-rows-and-banks.html

[72]

Raphael Spreitzer and Thomas Plos. 2013. Cache-Access Pattern Attack on Disaligned AES T-Tables. In COSADE .

[73]

Junko Takahashi, Toshinori Fukunaga, Kazumaro Aoki, and Hitoshi Fuji. 2013. Highly accurate key extraction method for access-driven cache attacks using correlation coefficient. In ACISP .

[74]

Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, and Raoul Strackx. 2018. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution. In USENIX Security Symposium .

[75]

Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2019. RIDL: Rogue In-flight Data Load. In S&P.

[76]

VMWare. 2018. Security considerations and disallowing inter-Virtual Machine Transparent Page Sharing (2080735). https://kb.vmware.com/s/article/2080735

[77]

Mario Werner, Thomas Unterluggauer, Lukas Giner, Michael Schwarz, Daniel Gruss, and Stefan Mangard. 2019. ScatterCache: Thwarting Cache Attacks via Cache Set Randomization. In USENIX Security Symposium .

[78]

Felix Wilhelm. 2016. PoC for breaking hypervisor ASLR using branch target buffer collisions. https://github.com/felixwilhelm/mario_baslr

[79]

Henry Wong. 2013. Intel Ivy Bridge Cache Replacement Policy . http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/

[80]

John C Wray. 1992. An analysis of covert timing channels . Journal of Computer Security, Vol. 1, 3--4 (1992), 219--232.

Digital Library

[81]

Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher Fletcher, Roy Campbell, and Josep Torrellas. 2019. Attack directories, not caches: Side channel attacks in a non-inclusive world. In S&P .

[82]

Yuval Yarom and Katrina Falkner. 2014. Flush

[83]

Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack. In USENIX Security Symposium .

[84]

Xiaokuan Zhang, Yuan Xiao, and Yinqian Zhang. 2016. Return-oriented flush-reload side channels on arm and their implications for android devices. In CCS.

[85]

Yinqian Zhang, Ari Juels, Michael K. Reiter, and Thomas Ristenpart. 2014. Cross-Tenant Side-Channel Attacks in PaaS Clouds. In CCS .

Cited By

Yuan JZhang JQiu PWei XLiu D(2024)A Survey of of Side-Channel Attacks and Mitigation for Processor InterconnectsApplied Sciences10.3390/app1415669914:15(6699)Online publication date: 31-Jul-2024
https://doi.org/10.3390/app14156699
Zhang JChen CCui JLi K(2024)Timing Side-Channel Attacks and Countermeasures in CPU MicroarchitecturesACM Computing Surveys10.1145/3645109Online publication date: 7-Feb-2024
https://doi.org/10.1145/3645109
Chen CCui JQu GZhang J(2024)Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk SynchronizationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.341425519(8066-8078)Online publication date: 2024
https://doi.org/10.1109/TIFS.2024.3414255
Show More Cited By

Index Terms

Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors
1. Security and privacy
  1. Security in hardware
    1. Hardware attacks and countermeasures
      1. Side-channel analysis and countermeasures
  2. Systems security
    1. Operating systems security

Recommendations

Heterogeneous way-size cache
ICS '06: Proceedings of the 20th annual international conference on Supercomputing

Set-associative cache architectures are commonly used. These caches consist of a number of ways, each of the same size. We have observed that the different ways have very different utilization, which motivates the design of caches with heterogeneous way ...
Architecting against Software Cache-Based Side-Channel Attacks

Using cache-like architectural components including data caches, instruction caches, or branch target buffers as a side channel, software cache-based side-channel attacks are able to derive secret keys used in cryptographic operations through legitimate ...
Data filter cache with word selection cache for low power embedded processor
RACS '13: Proceedings of the 2013 Research in Adaptive and Convergent Systems

Filter cache was proposed to reduce power consumption. The proposers inserted a small and fast cache, which is called Filter Cache, between core and L1 cache. Filter cache reduced the number of accesses to L1 cache and a significant power savings is ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ASIA CCS '20: Proceedings of the 15th ACM Asia Conference on Computer and Communications Security

October 2020

957 pages

ISBN:9781450367509

DOI:10.1145/3320269

General Chairs:
Hung-Min Sun
National Tsing Hua University, Taiwan
,
Shiuhpyng Shieh
National Chiao Tung University, Taiwan
,
Program Chairs:
Guofei Gu
Texas A&M University, USA
,
Giuseppe Ateniese
Stevens Institute of Technology, USA

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

SIGSAC: ACM Special Interest Group on Security, Audit, and Control

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 October 2020

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Österreichische Forschungsförderungsgesellschaft
Horizon 2020
Agence Nationale de la Recherche

Conference

ASIA CCS '20

Sponsor:

SIGSAC

ASIA CCS '20: The 15th ACM Asia Conference on Computer and Communications Security

October 5 - 9, 2020

Taipei, Taiwan

Acceptance Rates

Overall Acceptance Rate 418 of 2,322 submissions, 18%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

27
Total Citations
View Citations
562
Total Downloads

Downloads (Last 12 months)128
Downloads (Last 6 weeks)21

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Yuan JZhang JQiu PWei XLiu D(2024)A Survey of of Side-Channel Attacks and Mitigation for Processor InterconnectsApplied Sciences10.3390/app1415669914:15(6699)Online publication date: 31-Jul-2024
https://doi.org/10.3390/app14156699
Zhang JChen CCui JLi K(2024)Timing Side-Channel Attacks and Countermeasures in CPU MicroarchitecturesACM Computing Surveys10.1145/3645109Online publication date: 7-Feb-2024
https://doi.org/10.1145/3645109
Chen CCui JQu GZhang J(2024)Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk SynchronizationIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.341425519(8066-8078)Online publication date: 2024
https://doi.org/10.1109/TIFS.2024.3414255
Zhang XGong HChang RZhou Y(2024)RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic MappingIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.336886219(3758-3771)Online publication date: 2024
https://doi.org/10.1109/TIFS.2024.3368862
Gerlach LSchwarz SFaroß NSchwarz M(2024)Efficient and Generic Microarchitectural Hash-Function Recovery2024 IEEE Symposium on Security and Privacy (SP)10.1109/SP54263.2024.00028(3661-3678)Online publication date: 19-May-2024
https://doi.org/10.1109/SP54263.2024.00028
Liu YLi XZhang TLiu TGuo QZhang FWang J(2024)AVM-BTB: Adaptive and Virtualized Multi-level Branch Target Buffer2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00012(17-31)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00012
Lungu NDash BMishra MBarik LTripathy APatra S(2024)GPUSecBench: Evaluating the Cache Side-Channel Resilience of a GPU Security Execution Pipeline2024 Second International Conference on Intelligent Cyber Physical Systems and Internet of Things (ICoICI)10.1109/ICoICI62503.2024.10696012(564-571)Online publication date: 28-Aug-2024
https://doi.org/10.1109/ICoICI62503.2024.10696012
Zhang XZhang ZShen QWang WGao YYang ZZhang J(2024)SegScope: Probing Fine-grained Interrupts via Architectural Footprints2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00039(424-438)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00039
Saini GSomani G(2024)Resource Targeted Cybersecurity Attacks in Cloud Computing EnvironmentsResource Management in Distributed Systems10.1007/978-981-97-2644-8_9(169-188)Online publication date: 31-May-2024
https://doi.org/10.1007/978-981-97-2644-8_9
Hashemi MForte DGanji F(2024)Time Is Money, Friend! Timing Side-Channel Attack Against Garbled Circuit ConstructionsApplied Cryptography and Network Security10.1007/978-3-031-54776-8_13(325-354)Online publication date: 29-Feb-2024
https://doi.org/10.1007/978-3-031-54776-8_13
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents