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PAPS: power budget-aware pipeline scheduling for an embedded ReRAM-based accelerator

Authors:

Changchi Shuai,

Keni QiuAuthors Info & Claims

SEC '19: Proceedings of the 4th ACM/IEEE Symposium on Edge Computing

Pages 352 - 353

https://doi.org/10.1145/3318216.3363455

Published: 07 November 2019 Publication History

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Abstract

Many recent works have proposed to embed the emerging resistive switching random-access memory crossbar (ReRAM for short) to an edge device in Internet of Things (IoTs), such that those IoT nodes themselves are smart to process data rather than merely transmit raw data [1]. To acquire high throughput, multiple ReRAMs are scheduled in a pipeline fashion in the execution, but the peak power consumption of the ReRAM pipeline may probably exceed its power budget. Addressing the power issue, this paper proposes a Power budget-Aware Pipeline Scheduling (PAPS) scheme, which can achieve a well balanced and low power ReRAM pipeline.

References

[1]

Keni Qiu, Weiwen Chen, Yuanchao Xu, Lixue Xia, Yu Wang, and Zili Shao. 2018. A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN. In DATE'18. 1057--1062.

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[2]

Lixue Xia, Tianqi Tang, Wenqin Huangfu, Ming Cheng, Xiling Yin, Boxun Li, Yu Wang, and Huazhong Yang. 2016. Switched by Input: Power Efficient Structure for RRAM-Based Convolutional Neural Network. In DAC'16. 125:1--125:6.

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Published In

SEC '19: Proceedings of the 4th ACM/IEEE Symposium on Edge Computing

November 2019

455 pages

ISBN:9781450367332

DOI:10.1145/3318216

General Chairs:
Songqing Chen
George Mason University
,
Ryokichi Onishi
Toyota
,
Program Chairs:
Ganesh Ananthanarayanan
Microsoft Research
,
Qun Li
College of William & Mary

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Association for Computing Machinery

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Published: 07 November 2019

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National Natural Science Foundation of China
Beijing Advanced Innovation Center for Imaging Technology
Beijing Innovation Center for Future Chip

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SIGMOBILE

SEC '19: The Fourth ACM/IEEE Symposium on Edge Computing

November 7 - 9, 2019

Virginia, Arlington

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SEC '19 Paper Acceptance Rate 20 of 59 submissions, 34%;

Overall Acceptance Rate 40 of 100 submissions, 40%

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Power-Utility-Driven Write Management for MLC PCM

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Next high performance and low power flash memory package structure

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