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Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation

Authors:

Hao Yan,

Lei HeAuthors Info & Claims

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

Article No.: 150, Pages 1 - 6

https://doi.org/10.1145/3316781.3317863

Published: 02 June 2019 Publication History

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Abstract

"Curse of dimensionality" has become the major challenge for existing high-sigma yield analysis methods. In this paper, we develop a meta-model using Low-Rank Tensor Approximation (LRTA) to substitute expensive SPICE simulation. The polynomial degree of our LRTA model grows linearly with circuit dimension. This makes it especially promising for high-dimensional circuit problems. Our LRTA meta-model is solved efficiently with a robust greedy algorithm, and calibrated iteratively with an adaptive sampling method. Experiments on bit cell and SRAM column validate that proposed LRTA method outperforms other state-of-the-art approaches in terms of accuracy and efficiency.

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Cited By

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Gao ZZhang DDaniel LBoning DDe V(2024)NOFIS: Normalizing Flow for Rare Circuit Failure AnalysisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658459(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658459
Dou ZCheng MJia MWang PDe V(2024)BNN-YEO: an efficient Bayesian Neural Network for yield estimation and optimizationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658242(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658242
Xing WLiu YFan WHe LDe V(2024)Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield EvaluationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657381(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657381
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Index Terms

Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation
1. Hardware
  1. Robustness
    1. Fault tolerance
      1. Failure prediction

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Published In

DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

June 2019

1378 pages

ISBN:9781450367257

DOI:10.1145/3316781

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2019

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DAC '19

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SIGDA

DAC '19: The 56th Annual Design Automation Conference 2019

June 2 - 6, 2019

NV, Las Vegas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Gao ZZhang DDaniel LBoning DDe V(2024)NOFIS: Normalizing Flow for Rare Circuit Failure AnalysisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658459(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658459
Dou ZCheng MJia MWang PDe V(2024)BNN-YEO: an efficient Bayesian Neural Network for yield estimation and optimizationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3658242(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3658242
Xing WLiu YFan WHe LDe V(2024)Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield EvaluationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657381(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657381
Liu YXing W(2024)CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473819(386-391)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473819
Yin SDai GXing WTakahashi A(2023)High-Dimensional Yield Estimation Using Shrinkage Deep Features and Maximization of Integral Entropy ReductionProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567907(283-289)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567907
Shen SCao PLing MShi L(2023)A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319481242:4(1223-1234)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3194812
Xu HFan HJiang BChen JTong QZou X(2023)ML-Accelerated Yield Analysis Framework Using Regularization for Sparsity in High-Sigma and High-Dimensional ScenariosIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319236142:4(1161-1170)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3192361
Xin JYe ZWang YDeng DHu W(2023)Minimum Max-Rank Method for High-Sigma Yield Analysis2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218462(459-464)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218462
Liu YDai GCheng YKang WXing W(2023)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323689(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323689
Liu YDai GXing W(2023)Seeking the Yield Barrier: High-Dimensional SRAM Evaluation Through Optimal Manifold2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247952(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247952
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A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation

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