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Cache-optimal methods for bit-reversals

Authors:

Zhao Zhang,

Xiaodong ZhangAuthors Info & Claims

SC '99: Proceedings of the 1999 ACM/IEEE conference on Supercomputing

Pages 26 - es

https://doi.org/10.1145/331532.331558

Published: 01 January 1999 Publication History

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Cited By

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Elango KMuniandi K(2022)A Novel Digital Logic for Bit Reversal and Address Generations in FFT ComputationsWireless Personal Communications10.1007/s11277-022-10021-8128:3(1827-1838)Online publication date: 11-Sep-2022
https://doi.org/10.1007/s11277-022-10021-8
Gyanendra Raman BKaushik B(2020)Novel Bit-Reordering Circuit for Continuous-Flow Parallel FFT ArchitecturesIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.298489267:12(3392-3396)Online publication date: Dec-2020
https://doi.org/10.1109/TCSII.2020.2984892
Garrido MGrajal JGustafsson O(2011)Optimum Circuits for Bit ReversalIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2011.216414158:10(657-661)Online publication date: Oct-2011
https://doi.org/10.1109/TCSII.2011.2164141
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Cache-optimal methods for bit-reversals

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Published In

SC '99: Proceedings of the 1999 ACM/IEEE conference on Supercomputing

January 1999

1015 pages

ISBN:1581130910

DOI:10.1145/331532

General Chair:
Cherri Pancake

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 January 1999

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IEEE-CS

SC '99: International Conference for High Performance Computing, Networking, Storage and Analysis

November 14 - 19, 1999

Oregon, Portland, USA

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Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

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Cited By

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Elango KMuniandi K(2022)A Novel Digital Logic for Bit Reversal and Address Generations in FFT ComputationsWireless Personal Communications10.1007/s11277-022-10021-8128:3(1827-1838)Online publication date: 11-Sep-2022
Gyanendra Raman BKaushik B(2020)Novel Bit-Reordering Circuit for Continuous-Flow Parallel FFT ArchitecturesIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.298489267:12(3392-3396)Online publication date: Dec-2020
Garrido MGrajal JGustafsson O(2011)Optimum Circuits for Bit ReversalIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2011.216414158:10(657-661)Online publication date: Oct-2011
Jiang SZhang X(2005)Token-ordered LRUPerformance Evaluation10.1016/j.peva.2004.10.00260:1-4(5-29)Online publication date: 1-May-2005
D’Alberto PNicolau AVeidenbaum A(2004)A Data Cache with Dynamic MappingLanguages and Compilers for Parallel Computing10.1007/978-3-540-24644-2_28(436-450)Online publication date: 2004
(2003)Algorithms for memory hierarchiesundefinedOnline publication date: 1-Jan-2003
(2001)Dynamic Load Sharing With Unknown Memory Demands in ClustersProceedings of the The 21st International Conference on Distributed Computing Systems10.5555/876878.879245Online publication date: 16-Apr-2001
Songqing Chen Li Xiao Xiaodong Zhang (2001)Dynamic load sharing with unknown memory demands in clustersProceedings 21st International Conference on Distributed Computing Systems10.1109/ICDSC.2001.918939(109-118)Online publication date: 2001
Xiao LZhang XKubricht S(2000)Improving memory performance of sorting algorithmsACM Journal of Experimental Algorithmics10.1145/351827.3842455(3-es)Online publication date: 31-Dec-2000

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Prefix Reversals on Binary and Ternary Strings

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