poster

Analyzing networks-on-chip based deep neural networks

Authors:

Giuseppe Ascia,

Vincenzo Catania,

Salvatore Monteleone,

Maurizio Palesi,

Davide Patti,

John JoseAuthors Info & Claims

NOCS '19: Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip

Article No.: 23, Pages 1 - 2

https://doi.org/10.1145/3313231.3352375

Published: 17 October 2019 Publication History

Get Access

Abstract

One of the most promising architectures for performing deep neural network inferences on resource-constrained embedded devices is based on massive parallel and specialized cores interconnected by means of a Network-on-Chip (NoC). In this paper, we extensively evaluate NoC-based deep neural network accelerators by exploring the design space spanned by several architectural parameters. We show how latency is mainly dominated by the on-chip communication whereas energy consumption is mainly accounted by memory (both on-chip and off-chip).

References

[1]

Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, Yutaka Nakamura ans Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan Jackson, and Dharmendra S. Modha. 2015. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 10 (Oct 2015), 1537--1557.

Digital Library

Google Scholar

[2]

Lukas Cavigelli and Luca Benini. 2017. Origami: A 803-GOp/s/W Convolutional Network Accelerator. IEEE Transactions on Circuits and Systems for Video Technology 27, 11 (Nov 2017), 2461--2475.

Crossref

Google Scholar

[3]

Tianshi Chen, Zidong Du, Ninghui Sun, Jia Wang, Chengyong Wu, Yunji Chen, and Oliver Temam. 2014. DianNao: A Small-footprint High-throughput Accelerator for Ubiquitous Machine-learning. In International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, New York, NY, USA, 269--284.

Digital Library

Google Scholar

[4]

Francesco Conti, Pasquale Davide Schiavone, and Luca Benini. 2018. XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 11 (Nov 2018), 2940--2951.

Google Scholar

[5]

Alex Krizhevsky, Ilya Sutskever, and Geoffrey E. Hinton. 2017. ImageNet classification with deep convolutional neural networks. Commun. ACM 60, 6 (Jun 2017), 84--90.

Digital Library

Google Scholar

[6]

Dmitri Vainbrand and Ran Ginosar. 2010. Network-on-Chip Architectures for Neural Networks. In ACM/IEEE International Symposium on Networks-on-Chip. IEEE, -, 135--144.

Google Scholar

[7]

Ying Wang, Jie Xu, Yinhe Han, Huawei Li, and Xiaowei Li. 2016. DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family. In Proceedings of the 53rd Annual Design Automation Conference (DAC '16). ACM, New York, NY, USA, Article 110, 6 pages.

Digital Library

Google Scholar

[8]

Kaiwei Zou, Ying Wang, Huawei Li, and Xiaowei Li. 2019. Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. In IEEE/ACM Proceedings of Design, Automation and Test in Europe conference (DATE). IEEE, -, 1172--1177.

Google Scholar

Cited By

View all

Hsu CJian CTu ELee CChen G(2024)Real-Time Compressed Sensing for Joint Hyperspectral Image Transmission and Restoration for CubeSatIEEE Transactions on Geoscience and Remote Sensing10.1109/TGRS.2024.337882862(1-16)Online publication date: 2024
https://doi.org/10.1109/TGRS.2024.3378828
Trik MPour Mozaffari SBidgoli A(2021)Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC-Based Neuromorphic SystemsComputational Intelligence and Neuroscience10.1155/2021/83389032021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/8338903
Hsu CLin CKao CLin Y(2021)DCSN: Deep Compressed Sensing Network for Efficient Hyperspectral Data Transmission of Miniaturized SatelliteIEEE Transactions on Geoscience and Remote Sensing10.1109/TGRS.2020.303441459:9(7773-7789)Online publication date: Sep-2021
https://doi.org/10.1109/TGRS.2020.3034414
Show More Cited By

Recommendations

On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration

Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the ...
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Increasing application complexity and improvements in process technology have today enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on Chip (NoCs) have emerged as scalable communication fabrics that can support ...
A modular simulation framework for architectural exploration of on-chip interconnection networks
CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prevent time consuming design changes late in the design flow, we propose the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

NOCS '19: Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip

October 2019

161 pages

ISBN:9781450367004

DOI:10.1145/3313231

General Chairs:
Paul Bogdan
University of Southern California
,
Cristina Silvano
Politecnico di Milano

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

In-Cooperation

IEEE Circuits and Systems Society
IEEE-CEDA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 October 2019

Check for updates

Author Tags

Qualifiers

Poster

Conference

NOCS '19

Sponsor:

NOCS '19: International Symposium on Networks-on-Chip

October 17 - 18, 2019

New York, New York

Acceptance Rates

Overall Acceptance Rate 14 of 44 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
257
Total Downloads

Downloads (Last 12 months)15
Downloads (Last 6 weeks)1

Reflects downloads up to 28 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Hsu CJian CTu ELee CChen G(2024)Real-Time Compressed Sensing for Joint Hyperspectral Image Transmission and Restoration for CubeSatIEEE Transactions on Geoscience and Remote Sensing10.1109/TGRS.2024.337882862(1-16)Online publication date: 2024
https://doi.org/10.1109/TGRS.2024.3378828
Trik MPour Mozaffari SBidgoli A(2021)Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC-Based Neuromorphic SystemsComputational Intelligence and Neuroscience10.1155/2021/83389032021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/8338903
Hsu CLin CKao CLin Y(2021)DCSN: Deep Compressed Sensing Network for Efficient Hyperspectral Data Transmission of Miniaturized SatelliteIEEE Transactions on Geoscience and Remote Sensing10.1109/TGRS.2020.303441459:9(7773-7789)Online publication date: Sep-2021
https://doi.org/10.1109/TGRS.2020.3034414
Jayshree Seetharaman GPati D(2021)Energy consumption and performance comparison of DE optimization and PSO-based IP-core mapping technique for 2D and 3D network-on-chipSemiconductor Science and Technology10.1088/1361-6641/ac038c36:8(085015)Online publication date: 14-Jul-2021
https://doi.org/10.1088/1361-6641/ac038c
Mirmahaleh SReshadi MBagherzadeh NKhademzadeh A(2021)Data scheduling and placement in deep learning acceleratorCluster Computing10.1007/s10586-021-03355-8Online publication date: 10-Jul-2021
https://doi.org/10.1007/s10586-021-03355-8
Ascia GCatania VMonteleone SPalesi MPatti DJose JSalerno V(2020)Exploiting Data Resilience in Wireless Network-on-chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/337944816:2(1-27)Online publication date: 4-Apr-2020
https://dl.acm.org/doi/10.1145/3379448
Ascia GCatania VJose JMonteleone SPalesi MPatti D(2020)Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW50202.2020.00017(54-63)Online publication date: May-2020
https://doi.org/10.1109/IPDPSW50202.2020.00017

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration

Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors

A modular simulation framework for architectural exploration of on-chip interconnection networks