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Early Verification of ISA Extension Specifications using Deep Reinforcement Learning

Published: 07 September 2020 Publication History

Abstract

For IoT devices the demand in faster execution and at the same time lower energy consumption is a pressing problem. A very promising solution are Application-Specific Instruction-set Processors (ASIPs). They make use of custom instructions, which are added to the processor, forming the Instruction-Set Extension (ISE) of a given Instruction Set Architecture (ISA). While the selection process for the ISE is already challenging, an incorrect ISE specification leads to severe problems: errors and security vulnerabilities go undetected in the first formalization and in the worst case show up ultimately in the final implementation. In this paper, we propose an early verification approach for ISE specifications. Our novel approach is based on two ingredients: (i) Virtual Prototypes (VPs) to enable a rapid creation of an executable specification for the ISE; and (ii) Deep Reinforcement Learning (DRL) to search for ISE programs which violate the ISE specification intent. As case study we consider extensions of the RISC-V base ISA. We demonstrate the effectiveness of our approach for finding functional bugs in the executable specification of the ISE as well as specification gaps in the ISE leading to information leakage.

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References

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Cited By

View all
  • (2024)VerificationFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_4(107-152)Online publication date: 26-Mar-2024
  • (2021)EPEXProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461497(33-38)Online publication date: 22-Jun-2021

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cover image ACM Other conferences
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 September 2020

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Author Tags

  1. ISA extension
  2. deep reinforcement learning
  3. early verification

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  • Research-article

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  • German Federal Ministry of Education and Research (BMBF)

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GLSVLSI '20
GLSVLSI '20: Great Lakes Symposium on VLSI 2020
September 7 - 9, 2020
Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2024)VerificationFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_4(107-152)Online publication date: 26-Mar-2024
  • (2021)EPEXProceedings of the 2021 on Great Lakes Symposium on VLSI10.1145/3453688.3461497(33-38)Online publication date: 22-Jun-2021

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