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Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits

Published: 01 June 2000 Publication History

Abstract

A graph representation called Multi-Terminal Determinant Decision Diagrams (MTDDD's) is proposed for the semi-symbolic transfer functions of analog integrated circuits. With multiple numeric terminals (instead of only terminal 1 and terminal 0 in Determinant Decision Diagrams -- DDD's), MTDDD's can describe naturally numeric coefficients that arise from semi-symbolic analysis, where some circuit parameters are considered symbols and the others are given as numeric values. Similar to DDD's, MTDDD's are capable of representing a huge number of symbolic/semi-symbolic product terms in a compact manner. An efficient DDD-based algorithm is described to construct MTDDD's. Experimental results have demonstrated that semi-symbolic transfer functions for practical analog circuits like µA741 can be generated in less than a minute on a Pentium-II 450MHz PC.

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Cited By

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  • (2006)Timing analysis for full-custom circuits using symbolic DC formulationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85951025:9(1815-1830)Online publication date: 1-Sep-2006
  • (2004)Behavioural modelling of analog circuits by dynamic semi-symbolic analysis2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1329469(V-105-V-108)Online publication date: 2004
  • (2003)Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysisProceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.10.1109/ISCAS.2003.1206183(IV-660-IV-663)Online publication date: 2003
  • Show More Cited By

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          cover image ACM Conferences
          DAC '00: Proceedings of the 37th Annual Design Automation Conference
          June 2000
          819 pages
          ISBN:1581131879
          DOI:10.1145/337292
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Published: 01 June 2000

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          View all
          • (2006)Timing analysis for full-custom circuits using symbolic DC formulationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85951025:9(1815-1830)Online publication date: 1-Sep-2006
          • (2004)Behavioural modelling of analog circuits by dynamic semi-symbolic analysis2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1329469(V-105-V-108)Online publication date: 2004
          • (2003)Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysisProceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.10.1109/ISCAS.2003.1206183(IV-660-IV-663)Online publication date: 2003
          • (2001)Efficient DDD-based symbolic analysis of large linear analog circuitsProceedings of the 38th annual Design Automation Conference10.1145/378239.378384(139-144)Online publication date: 22-Jun-2001
          • (2001)Nonlinear Symbolic Network Analysis: Algorithms and Applications to RF CircuitsLow-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits10.1007/0-306-48089-1_7(131-154)Online publication date: 2001

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