research-article

Compiling Spiking Neural Networks to Neuromorphic Hardware

Authors:

Adarsha Balaji,

Nagarajan Kandasamy,

James ShacklefordAuthors Info & Claims

LCTES '20: The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems

Pages 38 - 50

https://doi.org/10.1145/3372799.3394364

Published: 16 June 2020 Publication History

Abstract

Machine learning applications that are implemented with spike-based computation model, e.g., Spiking Neural Network (SNN), have a great potential to lower the energy consumption when executed on a neuromorphic hardware. How- ever, compiling and mapping an SNN to the hardware is challenging, especially when compute and storage resources of the hardware (viz. crossbars) need to be shared among the neurons and synapses of the SNN. We propose an approach to analyze and compile SNNs on resource-constrained neuromorphic hardware, providing guarantees on key performance metrics such as execution time and throughput. Our approach makes the following three key contributions. First, we propose a greedy technique to partition an SNN into clusters of neurons and synapses such that each cluster can fit on to the resources of a crossbar. Second, we exploit the rich semantics and expressiveness of Synchronous Dataflow Graphs (SDFGs) to represent a clustered SNN and analyze its performance using Max-Plus Algebra, considering the available compute and storage capacities, buffer sizes, and communication bandwidth. Third, we propose a self-timed execution-based fast technique to compile and admit SNN-based applications to a neuromorphic hardware at run-time, adapting dynamically to the available resources on the hard- ware. We evaluate our approach with standard SNN-based applications and demonstrate a significant performance improvement compared to current practices.

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Cited By

Xiao CHe XYang ZXiao XWang YGong RTie JWang LXu W(2024)Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic ProcessorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334407043:5(1442-1455)Online publication date: May-2024
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Pham MD’Angiulli ADehnavi MChhabra R(2023)From Brain Models to Robotic Embodied Cognition: How Does Biological Plausibility Inform Neuromorphic Systems?Brain Sciences10.3390/brainsci1309131613:9(1316)Online publication date: 13-Sep-2023
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Index Terms

Compiling Spiking Neural Networks to Neuromorphic Hardware
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Data flow architectures
      2. Neural networks
2. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging languages and compilers
      2. Emerging tools and methodologies
    2. Biology-related information processing
      1. Neural systems

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cover image ACM Conferences

LCTES '20: The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems

June 2020

163 pages

ISBN:9781450370943

DOI:10.1145/3372799

General Chair:
Jingling Xue
UNSW Sydney, Australia
,
Program Chair:
Changhee Jung
Purdue University, USA

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https://doi.org/10.1109/TCAD.2023.3344070
Pedersen JAbreu SJobst MLenz GFra VBauer FMuir DZhou PVogginger BHeckel KUrgese GShankar SStewart TSheik SEshraghian J(2024)Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computingNature Communications10.1038/s41467-024-52259-915:1Online publication date: 16-Sep-2024
https://doi.org/10.1038/s41467-024-52259-9
Pham MD’Angiulli ADehnavi MChhabra R(2023)From Brain Models to Robotic Embodied Cognition: How Does Biological Plausibility Inform Neuromorphic Systems?Brain Sciences10.3390/brainsci1309131613:9(1316)Online publication date: 13-Sep-2023
https://doi.org/10.3390/brainsci13091316
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Varshika MCorradi FDas A(2022)Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging TrendsElectronics10.3390/electronics1110161011:10(1610)Online publication date: 18-May-2022
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