research-article

Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip

Authors:

Amaury Graillat,

Pascal Raymond,

Benoît Dupont de DinechinAuthors Info & Claims

RTNS '19: Proceedings of the 27th International Conference on Real-Time Networks and Systems

Pages 61 - 69

https://doi.org/10.1145/3356401.3356416

Published: 06 November 2019 Publication History

Abstract

We consider hard real-time applications running on many-core processor containing several clusters of cores linked by a Network-on-Chip (NoC). Communications are done via shared memory within a cluster and through the NoC for inter-cluster communication. We adopt the time-triggered paradigm, which is well-suited for hard real-time applications, and we consider data-flow applications, where communications are explicit.

We extend the AER (Acquisition/Execution/Restitution) execution model to account for all delays and interferences linked to communications, including the interference between the NoC interface and the memory. Indeed, for NoC communications, data is first read from the initiator's local memory, then sent over the NoC, and finally written to the local memory of the target cluster. Read and write accesses to transfer data between local memories may interfere with shared-memory communication inside a cluster, and, as far as we know, previous work did not take these interferences into account.

Building on previous work on deterministic network calculus and shared memory interference analysis, our method computes a static, time-triggered schedule for an application mapped on several clusters. This schedule guarantees that deadlines are met, and therefore provides a safe upper bound to the global worst-case response time.

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Cited By

Khalil KEldash OKumar ABayoumi M(2021)Self-Healing Router Approach for High-Performance Network-on-ChipIEEE Open Journal of Circuits and Systems10.1109/OJCAS.2021.30950002(485-496)Online publication date: 2021
https://doi.org/10.1109/OJCAS.2021.3095000
Dupont de Dinechin B(2021)A Qualitative Approach to Many‐core ArchitectureMulti‐Processor System‐on‐Chip 110.1002/9781119818298.ch2(27-51)Online publication date: 26-Mar-2021
https://doi.org/10.1002/9781119818298.ch2
Schuh MMaiza CGoossens JRaymond Pde Dinechin B(2020)A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory2020 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS49844.2020.00034(283-295)Online publication date: Dec-2020
https://doi.org/10.1109/RTSS49844.2020.00034

Index Terms

Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Redundancy
  2. Embedded and cyber-physical systems
    1. Embedded systems
    2. Robotics
2. Networks
  1. Network properties
    1. Network reliability

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cover image ACM Other conferences

RTNS '19: Proceedings of the 27th International Conference on Real-Time Networks and Systems

November 2019

221 pages

ISBN:9781450372237

DOI:10.1145/3356401

General Chair:
Jérôme Ermont
IRIT, ENSEEIHT, France
,
Program Chairs:
Ye-Qiong Song
LORIA - Université de Lorraine, France
,
Christopher Gill
Washington University in St. Louis

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 06 November 2019

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RTNS 2019

RTNS 2019: 27th International Conference on Real-Time Networks and Systems

November 6 - 8, 2019

Toulouse, France

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Cited By

Khalil KEldash OKumar ABayoumi M(2021)Self-Healing Router Approach for High-Performance Network-on-ChipIEEE Open Journal of Circuits and Systems10.1109/OJCAS.2021.30950002(485-496)Online publication date: 2021
https://doi.org/10.1109/OJCAS.2021.3095000
Dupont de Dinechin B(2021)A Qualitative Approach to Many‐core ArchitectureMulti‐Processor System‐on‐Chip 110.1002/9781119818298.ch2(27-51)Online publication date: 26-Mar-2021
https://doi.org/10.1002/9781119818298.ch2
Schuh MMaiza CGoossens JRaymond Pde Dinechin B(2020)A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory2020 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS49844.2020.00034(283-295)Online publication date: Dec-2020
https://doi.org/10.1109/RTSS49844.2020.00034

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