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Extending a CPU Design Project to Reinforce Learning

Published: 15 June 2020 Publication History

Abstract

A computer systems course using the "Nand2Tetris" materials has been taught in our institution for two years. Assignment work is based around extensions or variations of the projects provided. The challenge described in this paper was to develop a variation of project 5 that supported student's authentic learning of basic CPU design within time constrains and fitted with existing course materials. A 2-phase CPU design assignment was created that asked students to complete first the CPU design from the text book, and then complete an alternative CPU which replaced the D-register with a small register bank; each phase was weighted equally. The second phase reinforced the concepts learned in the first phase by making students identify the significant overlaps when decoding and generating control bits, as well as being exposed to hardware design choices at register level. Note files for project 5 can be easily sourced from MOOC resources, while this is not the case for the second phase as this was our own CPU design. Other alternative designs are possible, which can be used in rotation for this course. We could also ask students in advance CA courses to design and code their own extension of the Hack machine.

References

[1]
Martin Dick, Judy Sheard, Cathy Bareiss, Janet Carter, Donald Joyce, Trevor Harding, and Cary Laxer. 2002. Addressing Student Cheating: Definitions and Solutions. In Working Group Reports from 7th Annual Conference on Innovation and Technology in Computer Science Education (Aarhus, Denmark) (ITiCSE-WGR '02). ACM, New York, NY, USA, 172--184. https://doi.org/10.1145/960568.783000
[2]
N. Nisan and S. Schocken. 2005. The Elements of Computing Systems. MIT Press, Cambridge, MA.
[3]
Noam Nissam and Shimon Schocken. 2017 (accessed February 3, 2020). The official website of Nand to Tetris courses. https://www.nand2tetris.org
[4]
Shimon Schocken, Noam Nisan, and Michal Armoni. 2009. A Synthesis Course in Hardware Architecture, Compilers, and Software Engineering. SIGCSE Bull., Vol. 41, 1 (March 2009), 443--447. https://doi.org/10.1145/1539024.1509021

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  • (2023)Transpiling Nand2Tetris to VHDL for Teaching Digital LogicProceedings of the 2023 Conference on Innovation and Technology in Computer Science Education V. 210.1145/3587103.3594161(575-576)Online publication date: 29-Jun-2023

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cover image ACM Conferences
ITiCSE '20: Proceedings of the 2020 ACM Conference on Innovation and Technology in Computer Science Education
June 2020
615 pages
ISBN:9781450368742
DOI:10.1145/3341525
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

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Publication History

Published: 15 June 2020

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Author Tags

  1. CPU design
  2. assessment
  3. cheating preemption
  4. instruction decoding

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  • (2023)Transpiling Nand2Tetris to VHDL for Teaching Digital LogicProceedings of the 2023 Conference on Innovation and Technology in Computer Science Education V. 210.1145/3587103.3594161(575-576)Online publication date: 29-Jun-2023

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