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Fast Estimations of Failure Probability Over Long Time Spans

Published: 17 July 2018 Publication History

Abstract

Shrinking of device dimensions has undoubtedly enabled the very large scale integration of transistors on electronic chips. However, it has also brought to surface time-zero and time-dependent variation phenomena that degrade system's performance and threaten functional operation. Hence, the need to capture and describe these mechanisms, as well as effectively model their impact is crucial. To this extent, we follow existing models and propose a complete framework that evaluates failure probability of electronic components. To assess our framework, a case-study of packet-switched Network on Chip (NoC) routers is presented, studying the failure probability of its SRAM buffers.

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cover image ACM Conferences
NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures
July 2018
176 pages
ISBN:9781450358156
DOI:10.1145/3232195
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 July 2018

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Author Tags

  1. Aging
  2. BlackOut
  3. Reliability
  4. Variability

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NANOARCH '18 Paper Acceptance Rate 30 of 56 submissions, 54%;
Overall Acceptance Rate 55 of 87 submissions, 63%

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