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Dual-threshold directed execution progress maximization for nonvolatile processors

Published: 08 May 2018 Publication History

Abstract

To meet the needs of the Internet of Things (IoTs) devices, energy harvesting systems are proposed to power the systems instead of battery. Addressing the problem that harvested energy is unstable, nonvolatile processors (NVPs) have been proposed to hold intermediate data and avoid frequent program restarting from the beginning. However, NVPs often suffer a lot of waste on energy and system sources that can not be used for program execution owing to the frequent backup and recovery operations. To further improve the performance of NVPs, the paper proposes a dual-threshold method to maximize execution progress by enabling a system to hibernate to wait for power resumption instead of backing up data directly upon power interruptions. In particular, the optimal high and low thresholds, and the switches of system hibernation and backup, are discussed in details in order to achieve the goal of maximizing computation progress. The evaluation results show an average of up to 82.3% reduction on power failures and 1.5x speedup for forwarding progress by the proposed dual-threshold method compared to the conventional single threshold scheme.

References

[1]
Maolin's Home. 2017. How do capacitors store energy. http://www.360doc.com/content/17/1010/19/16534268_693842889.shtml. (2017).
[2]
W. Kang and Y. Ran et al. 2017. Modeling and Exploration of the Voltage-Controlled Magnetic Anisotropy Effect for the Next-Generation Low-Power and High-Speed MRAM Applications. IEEE Transactions on Nanotechnology 16, 3 (2017), 387--395.
[3]
X. Li and U. Dennis Heo et al. 2014. Rf-powered systems using steep-slope devices. In NEWCAS'14. 73--76.
[4]
Y. Liu and Z. Wang et al. 2016. 4.7 a 65nm ReRAM-enabled nonvolatile processor with 6x reduction in restore time and 4x higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. In ISSCC'16. 84--86.
[5]
K. Ma and Y. Zheng et al. 2015. Architecture exploration for ambient energy harvesting nonvolatile processors. In HPCA'15. 526--537.
[6]
C. Moser and L. Thiele et al. 2007. Adaptive Power Management in Energy Harvesting Systems. In DATE'07. 773--778.
[7]
J. Scott and L. H. Lee et al. 1998. Designing the low-power M*CORE architecture. In IEEE Power Driven Microarchitecture Workshop. 145--150.
[8]
F. Su and Y. Liu et al. 2017. A Ferroelectric Nonvolatile Processor with 46 μ s System-Level Wake-up Time and 14 μ s Sleep Time for Energy Harvesting Applications. TCAS-I'17 64, 3 (2017), 596--607.
[9]
S. Sudevalayam and P. Kulkarni. 2011. Energy Harvesting Sensor Nodes: Survey and Implications. IEEE Communications Surveys Tutorials 13, 3 (2011), 443--461.
[10]
The Daily Telegraph. 2016. Scientists develop "nerve dust": monitoring your health in your body. http://www.tech.163.com/16/0909/02/C0G621U300097U81.html. (2016).
[11]
Y. Wang and Y. Liu et al. 2012. A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. In ESSCIRC'12. 149--152.
[12]
M. Zhao and C. Fu et al. 2017. Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors. TCAD'17 36, 11 (2017), 1804--1816.
[13]
M. Zwerg and A. Baumann et al. 2011. An 82uA/MHz microcontroller with embedded FeRAM for energy-harvesting applications. In ISSCC'11. 334--336.

Cited By

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  • (2018)A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00023(70-75)Online publication date: Jul-2018

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Published In

cover image ACM Conferences
CF '18: Proceedings of the 15th ACM International Conference on Computing Frontiers
May 2018
401 pages
ISBN:9781450357616
DOI:10.1145/3203217
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 May 2018

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Author Tags

  1. NVP
  2. dual-threshold
  3. retention state

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CF '18
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CF '18: Computing Frontiers Conference
May 8 - 10, 2018
Ischia, Italy

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Overall Acceptance Rate 273 of 785 submissions, 35%

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  • (2018)A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00023(70-75)Online publication date: Jul-2018

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