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Data flow on a queue machine

Authors:

Bruno R. Preiss,

V. C. HamacherAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 13, Issue 3

Pages 342 - 351

https://doi.org/10.1145/327070.327367

Published: 01 June 1985 Publication History

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References

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Ben Abdallah ABen Abdallah A(2017)Parallelizing Compiler for Single and Multicore ComputingAdvanced Multicore Systems-On-Chip10.1007/978-981-10-6092-2_7(201-223)Online publication date: 12-Sep-2017
https://doi.org/10.1007/978-981-10-6092-2_7
Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
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Data flow on a queue machine

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 13, Issue 3

Special Issue: Proceedings of the 12th annual international symposium on Computer architecture (ISCA '85)

June 1985

396 pages

ISSN:0163-5964

DOI:10.1145/327070

Chairmen:
Thomas Gannon
Digital Equipment Corp.
,
Tilak Agerwala
IBM Research
,
Charles Freiman
IBM Research

Issue’s Table of Contents

ISCA '85: Proceedings of the 12th annual international symposium on Computer architecture
June 1985
428 pages
ISBN:0818606347
Chairmen:
Thomas Gannon
Digital Equipment Corp.
,
Tilak Agerwala
IBM Research
,
Charles Freiman
IBM Research

Publisher

Association for Computing Machinery

New York, NY, United States

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Published: 01 June 1985

Published in SIGARCH Volume 13, Issue 3

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Ben Abdallah ABen Abdallah A(2017)Parallelizing Compiler for Single and Multicore ComputingAdvanced Multicore Systems-On-Chip10.1007/978-981-10-6092-2_7(201-223)Online publication date: 12-Sep-2017
https://doi.org/10.1007/978-981-10-6092-2_7
Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Abderazek BCanedo AKuroda K(2009)Processor for Mobile ApplicationsHandbook of Research on Mobile Multimedia, Second Edition10.4018/978-1-60566-046-2.ch035(510-522)Online publication date: 2009
https://doi.org/10.4018/978-1-60566-046-2.ch035
Fernandes SOliveira BCosta MSilva I(2009)Processing while routing: a network-on-chip-based parallel systemIET Computers & Digital Techniques10.1049/iet-cdt.2008.00713:5(525)Online publication date: 2009
https://doi.org/10.1049/iet-cdt.2008.0071
Canedo AAbderazek BSowa M(2009)Efficient compilation for queue size constrained queue processorsParallel Computing10.1016/j.parco.2008.11.00435:4(213-225)Online publication date: 1-Apr-2009
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Canedo AAbderazek BSowa M(2009)Design and implementation of a queue compilerMicroprocessors & Microsystems10.1016/j.micpro.2008.09.00133:2(129-138)Online publication date: 1-Mar-2009
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Canedo AAbderazek BSowa M(2009)Compiler Support for Code Size Reduction Using a Queue-Based ProcessorTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_14(269-285)Online publication date: 22-Apr-2009
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Canedo ASowa MAbderazek B(2008)Quantitative Evaluation of Common Subexpression Elimination on Queue MachinesProceedings of the The International Symposium on Parallel Architectures, Algorithms, and Networks10.1109/I-SPAN.2008.25(25-30)Online publication date: 7-May-2008
https://dl.acm.org/doi/10.1109/I-SPAN.2008.25
Abderazek BCanedo AYoshinaga TSowa M(2008)The QC-2 parallel Queue processor architectureJournal of Parallel and Distributed Computing10.1016/j.jpdc.2007.08.00468:2(235-245)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1016/j.jpdc.2007.08.004
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The cyclic queue and the tandem queue

A multiserver retrial queue: regenerative stability analysis

A Two-Queue Polling Model with Two Priority Levels in the First Queue

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