research-article

Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA

Authors:

Ryutaro Doi,

Jaehoon Yu,

Masanori HashimotoAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/3240765.3240849

Published: 05 November 2018 Publication History

Abstract

FPGA that utilizes via-switches, which are a kind of nonvolatile resistive RAMs, for crossbar implementation is attracting attention due to higher integration density and performance. However, programming via-switches arbitrarily in a crossbar is not trivial since a programming current must be provided through signal wires that are shared by multiple via-switches. Consequently, depending on the previous programming status in sequential programming, unintentional switch programming may occur due to signal detour, which is called sneak path problem. This problem interferes the reconfiguration of via-switch FPGA, and hence countermeasures for sneak path problem are indispensable. This paper identifies the circuit status that causes sneak path problem and proposes a sneak path avoidance method that gives sneak path free programming order of via-switches in a crossbar. We prove that sneak path free programming order necessarily exists for arbitrary on-off patterns in a crossbar as long as no loops exist, and also validate the proof and the proposed method with simulation-based evaluation. Thanks to the proposed method, any practical configurations of via-switch FPGA can be successfully programmed without sneak path problem.

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Liu WChen CXiao KFeng MZhang HZhai G(2024)Sneak Circuit Analysis Covering Interface Circuits in Spacecraft Integrated Chips while Considering Faults2024 6th International Conference on System Reliability and Safety Engineering (SRSE)10.1109/SRSE63568.2024.10772492(222-228)Online publication date: 11-Oct-2024
https://doi.org/10.1109/SRSE63568.2024.10772492
Hashimoto MBai XBanno NTada MSakamoto TYu JDoi ROnodera HImagawa TOchi HWakabayashi KMitsuyama YSugibayashi T(2022)Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computationJapanese Journal of Applied Physics10.35848/1347-4065/ac6b8161:SM(SM0804)Online publication date: 23-Jun-2022
https://doi.org/10.35848/1347-4065/ac6b81
Chen Y(2021)Self-Rectified Graphite-Based Reprogrammable One-Time Programmable (RS-OTP) Memory for Embedded ApplicationsFrontiers in Nanotechnology10.3389/fnano.2021.7722343Online publication date: 22-Nov-2021
https://doi.org/10.3389/fnano.2021.772234
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Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
1. Hardware
  1. Integrated circuits

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2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

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Published: 05 November 2018

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Liu WChen CXiao KFeng MZhang HZhai G(2024)Sneak Circuit Analysis Covering Interface Circuits in Spacecraft Integrated Chips while Considering Faults2024 6th International Conference on System Reliability and Safety Engineering (SRSE)10.1109/SRSE63568.2024.10772492(222-228)Online publication date: 11-Oct-2024
https://doi.org/10.1109/SRSE63568.2024.10772492
Hashimoto MBai XBanno NTada MSakamoto TYu JDoi ROnodera HImagawa TOchi HWakabayashi KMitsuyama YSugibayashi T(2022)Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computationJapanese Journal of Applied Physics10.35848/1347-4065/ac6b8161:SM(SM0804)Online publication date: 23-Jun-2022
https://doi.org/10.35848/1347-4065/ac6b81
Chen Y(2021)Self-Rectified Graphite-Based Reprogrammable One-Time Programmable (RS-OTP) Memory for Embedded ApplicationsFrontiers in Nanotechnology10.3389/fnano.2021.7722343Online publication date: 22-Nov-2021
https://doi.org/10.3389/fnano.2021.772234
Doi RYu JHashimoto M(2020)Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.296033139:10(2572-2587)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2960331

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Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

Automated synthesis of compact crossbars for sneak-path based in-memory computing

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

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