research-article

Exploring Machine Learning for Thread Characterization on Heterogeneous Multiprocessors

Authors:

Vinicius Petrucci,

Daniel MosséAuthors Info & Claims

ACM SIGOPS Operating Systems Review, Volume 51, Issue 1

Pages 113 - 123

https://doi.org/10.1145/3139645.3139664

Published: 11 September 2017 Publication History

Abstract

We introduce a thread characterization method that explores hardware performance counters and machine learning techniques to automate estimating workload execution on heterogeneous processors. We show that our characterization scheme achieves higher accuracy when predicting performance indicators, such as instructions per cycle and last-level cache misses, commonly used to determine the mapping of threads to processor types at runtime. We also show that support vector regression achieves higher accuracy when compared to linear regression, and has very low (1%) overhead. The results presented in this paper can provide a foundation for advanced investigations and interesting new directions in intelligent thread scheduling and power management on multiprocessors.

References

[1]

Octave-forge - extra packages for gnu octave.

[2]

perfmon2: the hardware-based performance monitoring interface for linux.

[3]

M. F. Akay and I. Abaskele. Predicting the performance measures of an optical distributed shared memory multiprocessor by using support vector regression. Expert Systems with Applications, 37(9):6293--6301, 2010.

Digital Library

[4]

R. W. S. Alan V. Oppenheim. Discrete-Time Signal Processing. Prentice Hall, 2009.

Digital Library

[5]

ARM. big.LITTLE processing, 2011.

[6]

J. L. Berral, R. Gavalda, and J. Torres. Adaptive scheduling on power-aware managed data-centers using machine learning. In Proceedings of the 2011 IEEE/ACM 12th International Conference on Grid Computing, GRID '11, pages 66--73, Washington, DC, USA, 2011. IEEE Computer Society.

Digital Library

[7]

C. M. Bishop. Pattern Recoginition and Machine Learning. Springer, 2007.

[8]

C.-C. Chang and C.-J. Lin. LIBSVM: A library for support vector machines. ACM Transactions on Intelligent Systems and Technology, 2:27:1--27:27, 2011. Software available at http://www.csie.ntu.edu.tw/~cjlin/libsvm.

Digital Library

[9]

N. Chitlur, G. Srinivasa, S. Hahn, P. K. Gupta, D. Reddy, D. Koufaty, P. Brett, A. Prabhakaran, L. Zhao, N. Ijih, S. Subhaschandra, S. Grover, X. Jiang, and R. Iyer. Quickia: Exploring heterogeneous architectures on real prototypes. In High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, 2012.

Digital Library

[10]

E. Ipek, O. Mutlu, J. F. Martínez, and R. Caruana. Self-optimizing memory controllers: A reinforcement learning approach. In Proceedings of the 35th Annual International Symposium on Computer Architecture, ISCA '08, pages 39--50, Washington, DC, USA, 2008. IEEE Computer Society.

Digital Library

[11]

C. Isci, G. Contreras, and M. Martonosi. Live, runtime phase monitoring and prediction on real systems with application to dynamic power management. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 39, pages 359--370, 2006.

Digital Library

[12]

H. Jung and M. Pedram. Supervised learning based power management for multicore processors. Trans. Comp.-Aided Des. Integ. Cir. Sys., 29(9):1395--1408, Sept. 2010.

Digital Library

[13]

D. Koufaty, D. Reddy, and S. Hahn. Bias scheduling in heterogeneous multi-core architectures. In EuroSys'10.

Digital Library

[14]

M. Y. Lim, A. Porterfield, and R. Fowler. Softpower: fine-grain power estimations using performance counters. In Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, HPDC '10, pages 308--311, New York, NY, USA, 2010. ACM.

Digital Library

[15]

J. L. Myers and A. D. Well. Research design and statistical analysis. Lawrence Erlbaum, 2002.

[16]

V. Petrucci, M. A. Laurenzano, J. Doherty, Y. Zhang, D. Mosse, J. Mars, and L. Tang. Octopus-man: Qos-driven task management for heterogeneous multicores in warehouse-scale computers. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pages 246--258, Feb 2015.

[17]

V. Petrucci, O. Loques, and D. Mossé. Lucky scheduling for energy-efficient heterogeneous multi-core systems. In HotPower'12.

Digital Library

[18]

V. Petrucci, O. Loques, D. Mosse', R. Melhem, N. Gazala, and S. Gobriel. Thread assignment optimization with real-time performance and memory bandwidth guarantees for energy-efficient heterogeneous multi-core systems. In RTAS'2012, Beijing, China, 2012.

Digital Library

[19]

V. Petrucci, O. Loques, D. Mossé, R. Melhem, N. A. Gazala, and S. Gobriel. Energy-efficient thread assignment optimization for heterogeneous multicore systems. ACM Trans. Embed. Comput. Syst., 14(1):15:1--15:26, Jan. 2015.

Digital Library

[20]

J. C. Saez, A. Fedorova, D. Koufaty, and M. Prieto. Leveraging Core Specialization via OS Scheduling to Improve Performance on Asymmetric Multicore Systems. ACM Trans. Comput. Syst., 30(2):6:1--6:38, Apr. 2012.

Digital Library

[21]

R. Sarikaya, C. Isci, and A. Buyuktosunoglu. Program behavior prediction using a statistical metric model. In Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems, SIGMETRICS '10, pages 371--372, New York, NY, USA, 2010. ACM.

Digital Library

[22]

A. Savitzky and M. J. E. Golay. Smoothing and differentiation of data by simplified least squares procedures. Analytical Chemistry, 36(8):1627--1639, 1964.

[23]

T. Sherwood, S. Sair, and B. Calder. Phase tracking and prediction. In Proceedings of the 30th annual international symposium on Computer architecture, ISCA '03, pages 336--349, New York, NY, USA, 2003. ACM.

Digital Library

[24]

K. Singh, M. Bhadauria, and S. A. McKee. Real time power estimation and thread scheduling via performance counters. SIGARCH Comput. Archit. News, 37(2):46--55, July 2009.

Digital Library

[25]

A. J. Smola and B. Schölkopf. A tutorial on support vector regression. Statistics and Computing, 14(3):199--222, Aug. 2004.

Digital Library

[26]

D. C. Snowdon, E. Le Sueur, S. M. Petters, and G. Heiser. Koala: a platform for os-level power management. In Proceedings of the 4th ACM European conference on Computer systems, EuroSys '09, pages 289--302, New York, NY, USA, 2009. ACM.

Digital Library

[27]

Z. Wang, A. Bovik, H. Sheikh, and E. Simoncelli. Image quality assessment: from error visibility to structural similarity. Image Processing, IEEE Transactions on, 13(4):600 --612, april 2004.

Digital Library

[28]

M. Welling. Support vector machines. A note explaining SVM, 2005.

[29]

M. Welling. Support vector regression. A note explaining SVR, 2005.

[30]

Y. Zhu, M. Halpern, and V. J. Reddi. The role of the cpu in energy-efficient mobile web browsing. Micro, IEEE, 35(1):26--33, 2015.

[31]

Y. Zhu and V. J. Reddi. High-performance and energy-efficient mobile web browsing on big/little systems. Proceedings of the 19th High Performance Computer Architecture, 2013.

Digital Library

Cited By

Encinas JRodríguez AOtero Ade la Torre E(2024)Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloadsMicroprocessors and Microsystems10.1016/j.micpro.2024.105050(105050)Online publication date: Apr-2024
https://doi.org/10.1016/j.micpro.2024.105050
Allaqband SNazish MAllaqband SBashir JBanday M(2024)An efficient machine learning based CPU scheduler for heterogeneous multicore processorsInternational Journal of Information Technology10.1007/s41870-024-01936-5Online publication date: 24-May-2024
https://doi.org/10.1007/s41870-024-01936-5
Sivaramakrishnan RSenthilkumar G(2023)A Deep Learning Framework for Microarchitecture Independent Workload Characterization Technique for Multi-core Asymmetric Embedded SystemsSN Computer Science10.1007/s42979-023-01909-84:5Online publication date: 30-Jun-2023
https://dl.acm.org/doi/10.1007/s42979-023-01909-8
Show More Cited By

Index Terms

Exploring Machine Learning for Thread Characterization on Heterogeneous Multiprocessors
1. Computing methodologies
  1. Machine learning
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

Index terms have been assigned to the content through auto-classification.

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Information & Contributors

Information

Published In

cover image ACM SIGOPS Operating Systems Review

ACM SIGOPS Operating Systems Review Volume 51, Issue 1

Special Topics

August 2017

123 pages

ISSN:0163-5980

DOI:10.1145/3139645

Editors:
Mark Silberstein
Technion, Hafia, Israel
,
Christopher J. Rossbach
Stop D9500, Austin, TX

Issue’s Table of Contents

Copyright © 2017 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2017

Published in SIGOPS Volume 51, Issue 1

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Cited By

Encinas JRodríguez AOtero Ade la Torre E(2024)Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloadsMicroprocessors and Microsystems10.1016/j.micpro.2024.105050(105050)Online publication date: Apr-2024
https://doi.org/10.1016/j.micpro.2024.105050
Allaqband SNazish MAllaqband SBashir JBanday M(2024)An efficient machine learning based CPU scheduler for heterogeneous multicore processorsInternational Journal of Information Technology10.1007/s41870-024-01936-5Online publication date: 24-May-2024
https://doi.org/10.1007/s41870-024-01936-5
Sivaramakrishnan RSenthilkumar G(2023)A Deep Learning Framework for Microarchitecture Independent Workload Characterization Technique for Multi-core Asymmetric Embedded SystemsSN Computer Science10.1007/s42979-023-01909-84:5Online publication date: 30-Jun-2023
https://dl.acm.org/doi/10.1007/s42979-023-01909-8
Saez JPrieto-Matias MSerafini MXu H(2022)Evaluation of the Intel thread director technology on an Alder Lake processorProceedings of the 13th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3546591.3547532(61-67)Online publication date: 23-Aug-2022
https://dl.acm.org/doi/10.1145/3546591.3547532
Xu VMcShane LMosse D(2021)LUSH: Lightweight Framework for User-level Scheduling in Heterogeneous Multicores2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC51149.2021.00065(396-404)Online publication date: Dec-2021
https://doi.org/10.1109/MCSoC51149.2021.00065
Rapp MPathania AMitra THenkel J(2020)Neural Network-based Performance Prediction for Task Migration on S-NUCA Many-CoresIEEE Transactions on Computers10.1109/TC.2020.3023022(1-1)Online publication date: 2020
https://doi.org/10.1109/TC.2020.3023022
B GSelvakumar J(2020)Appropriate allocation of workloads on performance asymmetric multicore architectures via deep learning algorithmsMicroprocessors & Microsystems10.1016/j.micpro.2020.10299673:COnline publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1016/j.micpro.2020.102996
Gamatié AAn XZhang YKang ASassatelli G(2019)Empirical Model-Based Performance Prediction for Application Mapping on Multicore ArchitecturesJournal of Systems Architecture10.1016/j.sysarc.2019.06.001Online publication date: Jun-2019
https://doi.org/10.1016/j.sysarc.2019.06.001

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