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Designing scalable FPGA architectures using high-level synthesis

Authors:

Johannes de Fine Licht,

Michaela Blott,

Torsten HoeflerAuthors Info & Claims

PPoPP '18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

Pages 403 - 404

https://doi.org/10.1145/3178487.3178527

Published: 10 February 2018 Publication History

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Abstract

Massive spatial parallelism at low energy gives FPGAs the potential to be core components in large scale high performance computing (HPC) systems. In this paper we present four major design steps that harness high-level synthesis (HLS) to implement scalable spatial FPGA algorithms. To aid productivity, we introduce the open source library hlslib to complement HLS. We evaluate kernels designed with our approach on an FPGA accelerator board, demonstrating high performance and board utilization with enhanced programmer productivity. By following our guidelines, programmers can use HLS to develop efficient parallel algorithms for FPGA, scaling their implementations with increased resources on future hardware.

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Cited By

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Brown N(2024)Domain Specific Abstractions for the Development of Fast-by-Construction Dataflow Codes on FPGAsChips10.3390/chips30400173:4(334-360)Online publication date: 4-Oct-2024
https://doi.org/10.3390/chips3040017
Rodriguez-Canal GBrown NJamieson MBauer ELydike AGrosser T(2023)Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGAProceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624543(556-565)Online publication date: 12-Nov-2023
https://dl.acm.org/doi/10.1145/3624062.3624543
Denzler AOliveira GHajinazar NBera RSingh GGomez-Luna JMutlu O(2023)Casper: Accelerating Stencil Computations Using Near-Cache ProcessingIEEE Access10.1109/ACCESS.2023.325200211(22136-22154)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3252002
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Index Terms

Designing scalable FPGA architectures using high-level synthesis
1. Computing methodologies
  1. Parallel computing methodologies
    1. Parallel programming languages
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Information

Published In

PPoPP '18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

February 2018

442 pages

ISBN:9781450349826

DOI:10.1145/3178487

General Chair:
Andreas Krall
Vienna University of Technology, Austria
,
Program Chair:
Thomas R. Gross
ETH Zürich, Switzerland

ACM SIGPLAN Notices Volume 53, Issue 1
PPoPP '18
January 2018
426 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/3200691
Editor:
Matthew Fluet
Rodchester Institude of Technology
Issue’s Table of Contents

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

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Published: 10 February 2018

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PPoPP '18

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PPoPP '18: 23nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

February 24 - 28, 2018

Vienna, Austria

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Overall Acceptance Rate 230 of 1,014 submissions, 23%

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Brown N(2024)Domain Specific Abstractions for the Development of Fast-by-Construction Dataflow Codes on FPGAsChips10.3390/chips30400173:4(334-360)Online publication date: 4-Oct-2024
https://doi.org/10.3390/chips3040017
Rodriguez-Canal GBrown NJamieson MBauer ELydike AGrosser T(2023)Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGAProceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624543(556-565)Online publication date: 12-Nov-2023
https://dl.acm.org/doi/10.1145/3624062.3624543
Denzler AOliveira GHajinazar NBera RSingh GGomez-Luna JMutlu O(2023)Casper: Accelerating Stencil Computations Using Near-Cache ProcessingIEEE Access10.1109/ACCESS.2023.325200211(22136-22154)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3252002
Singh GDiamantopoulos DGómez-Luna JHagleitner CStuijk SCorporaal HMutlu O(2022)Accelerating Weather Prediction using Near-Memory Reconfigurable FabricACM Transactions on Reconfigurable Technology and Systems10.1145/3501804Online publication date: 9-Feb-2022
https://doi.org/10.1145/3501804
Wyrzykowski RDeelman ERojek KHalbiniak KKuczynski L(2021)CFD code adaptation to the FPGA architectureInternational Journal of High Performance Computing Applications10.1177/109434202097246135:1(33-46)Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1177/1094342020972461
Singh GDiamantopoulos DHagleitner CGomez-Luna JStuijk SMutlu OCorporaal H(2020)NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00014(9-17)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00014
Eran HZeno LIstvan ZSilberstein M(2019)Design Patterns for Code Reuse in HLS Packet Processing Pipelines2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2019.00036(208-217)Online publication date: Apr-2019
https://doi.org/10.1109/FCCM.2019.00036
Denzler AOliveira GHajinazar NBera RSingh GGómez-Luna JMutlu O(2023)Casper: Accelerating Stencil Computations Using Near-Cache ProcessingIEEE Access10.1109/ACCESS.2023.325200211(22136-22154)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3252002
Bartel SKorch M(2021)Generation of logic designs for efficiently solving ordinary differential equations on field programmable gate arraysSoftware: Practice and Experience10.1002/spe.304353:1(27-52)Online publication date: 19-Oct-2021
https://doi.org/10.1002/spe.3043
Huang LLi DWang KGao TTavares A(2020)A Survey on Performance Optimization of High-Level Synthesis ToolsJournal of Computer Science and Technology10.1007/s11390-020-9414-835:3(697-720)Online publication date: 29-May-2020
https://doi.org/10.1007/s11390-020-9414-8
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