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High performance integrated Prolog processor IPP

Authors:

S. Abe,

T. Bandoh,

S. Yamaguchi,

K. Kurosawa,

K. KiriyamaAuthors Info & Claims

ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

Pages 100 - 107

https://doi.org/10.1145/30350.30362

Published: 01 June 1987 Publication History

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Abstract

To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed.

A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an IPP architecture is presented. Based on the Prolog instruction set, which is an extension of Warren's, the Prolog compiler introduces new functions such as indexing by the optimal argument and global register assignment across determinate built-in predicates.

The performance of the IPP for the append program is 1 million logical inferences per second, which is the highest possible for a sequential processor. In the 8-queen program a considerable speed-up is obtained by the new functions.

References

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D.H.Warren, "An Abstract Prolog Instruction Set," Technical Note 309, Artificial Intelligence Center, SRI International, October 1983.

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R.Nakazaki et al., "Design of a High-speed Prolog Machine(HPM)," Proceedings of the 12th International symposium on Computer Architecture, June 1985, pp 191-197.

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T.P.Dobry et al., "Performance Studies of a Prolog Machine Architecture," ibid., pp 180-190.

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Cited By

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Shin DBerra P(2009)Computer architectures for logic-oriented data/knowledge bases1The Knowledge Engineering Review10.1017/S02698889000047204:01(1)Online publication date: 7-Jul-2009
https://doi.org/10.1017/S0269888900004720
Dong Wang Kobayashi HNakamura T(1995)Design and performance measurements of an execution model for the parallel processing of Prolog programsProceedings 1st International Conference on Algorithms and Architectures for Parallel Processing10.1109/ICAPP.1995.472252(650-658)Online publication date: 1995
https://doi.org/10.1109/ICAPP.1995.472252
Ng K(1993)Design and simulation of the LOW RISC II/sub R/Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation10.1109/TENCON.1993.319926(53-56)Online publication date: 1993
https://doi.org/10.1109/TENCON.1993.319926
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High performance integrated Prolog processor IPP

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Published In

ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

June 1987

321 pages

ISBN:0818607769

DOI:10.1145/30350

Editor:
D. St. Clair

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1987

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ISCA87

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SIGARCH

ISCA87: The 14th Annual International Symposium on Computer Architecture

June 2 - 5, 1987

Pennsylvania, Pittsburgh, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

View all

Shin DBerra P(2009)Computer architectures for logic-oriented data/knowledge bases1The Knowledge Engineering Review10.1017/S02698889000047204:01(1)Online publication date: 7-Jul-2009
https://doi.org/10.1017/S0269888900004720
Dong Wang Kobayashi HNakamura T(1995)Design and performance measurements of an execution model for the parallel processing of Prolog programsProceedings 1st International Conference on Algorithms and Architectures for Parallel Processing10.1109/ICAPP.1995.472252(650-658)Online publication date: 1995
https://doi.org/10.1109/ICAPP.1995.472252
Ng K(1993)Design and simulation of the LOW RISC II/sub R/Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation10.1109/TENCON.1993.319926(53-56)Online publication date: 1993
https://doi.org/10.1109/TENCON.1993.319926
Nakashima HTakeda YNakajima KAndou HFurutani K(1990)A pipelined microprocessor for logic programming languagesProceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors10.1109/ICCD.1990.130252(355-359)Online publication date: 1990
https://doi.org/10.1109/ICCD.1990.130252
Sibai FWatson KLu M(1990)A Parallel Unification MachineIEEE Micro10.1109/40.5772810:4(21-33)Online publication date: 1-Jul-1990
https://dl.acm.org/doi/10.1109/40.57728
Sibai FWatson LLu M(1989)Design and performance measurements of a parallel machine for the unification algorithmACM SIGMICRO Newsletter10.1145/75395.7539820:3(21-30)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75395.75398
Sibai FWatson LLu M(1989)Design and performance measurements of a parallel machine for the unification algorithmProceedings of the 22nd annual workshop on Microprogramming and microarchitecture10.1145/75362.75398(21-30)Online publication date: 1-Aug-1989
https://dl.acm.org/doi/10.1145/75362.75398
Morioka MYamaguchi SBandoh T(1989)Evaluation of memory system for integrated Prolog processor IPPACM SIGARCH Computer Architecture News10.1145/74926.7494917:3(203-210)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/74926.74949
Morioka MYamaguchi SBandoh TSyre J(1989)Evaluation of memory system for integrated Prolog processor IPPProceedings of the 16th annual international symposium on Computer architecture10.1145/74925.74949(203-210)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/74925.74949
Sibai FWatson KLu M(1989)A parallel unification coprocessor[Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence10.1109/TAI.1989.65374(608-615)Online publication date: 1989
https://doi.org/10.1109/TAI.1989.65374
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Architecture of high performance integrated Prolog processor IPP

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