research-article

One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory

Authors:

Guangjun WenAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 13, Issue 2

Article No.: 25, Pages 1 - 18

https://doi.org/10.1145/3012002

Published: 03 February 2017 Publication History

Abstract

A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three other resistors corresponding to unselected cells that contribute to the sneak-path. Two sensing voltages with equal potential are applied to three terminals of the network. One is for sensing the resistance of the selected cell; the other is for creating zero-voltage drop across one of the three resistors, which connects the sneak-path to the selected cell. This effectively suppresses the current injected by the sneak-path to the selected cell-sensing loop. This work also proposes a cost-effective data-encoding circuit that guarantees that at least half of the memory cells are in a high-resistance state, which further minimizes sneak-path current. The impact of key design parameters, such as sensing voltage, switch on-resistance, and the ratio of memory cell resistances in different states, as well as nonideal effects are investigated. Equations for estimating the maximum array size to share a single read circuit are derived. The effectiveness of the proposed design has been validated via circuit simulations. Impacts of the word-/bit-line resistance are also analyzed.

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Cited By

Chakraborty AGupta PSingh RDas RRahaman H(2021)BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)Integration10.1016/j.vlsi.2021.08.002Online publication date: Aug-2021
https://doi.org/10.1016/j.vlsi.2021.08.002
Chakraborty ASaurabh VGupta PKumar RMajumdar SDas SRahaman H(2018)In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)Integration10.1016/j.vlsi.2018.12.005Online publication date: Dec-2018
https://doi.org/10.1016/j.vlsi.2018.12.005

Index Terms

One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 13, Issue 2

Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers

April 2017

377 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3014160

Editor:
Yuan Xie
University of California, Santa Barbara, USA

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Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 February 2017

Accepted: 01 October 2016

Revised: 01 June 2016

Received: 01 March 2016

Published in JETC Volume 13, Issue 2

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Guangdong Province Science and Technology Program
Fundamental Research Funds for the Central Universities

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Cited By

Chakraborty AGupta PSingh RDas RRahaman H(2021)BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)Integration10.1016/j.vlsi.2021.08.002Online publication date: Aug-2021
https://doi.org/10.1016/j.vlsi.2021.08.002
Chakraborty ASaurabh VGupta PKumar RMajumdar SDas SRahaman H(2018)In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)Integration10.1016/j.vlsi.2018.12.005Online publication date: Dec-2018
https://doi.org/10.1016/j.vlsi.2018.12.005

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