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Cited By

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Rao DWilsey PNicol DFujimoto R(2006)Applying parallel, dynamic-resolution simulations to accelerate VLSI power estimationProceedings of the 38th conference on Winter simulation10.5555/1218112.1218242(694-702)Online publication date: 3-Dec-2006
https://dl.acm.org/doi/10.5555/1218112.1218242
Rao DWilsey P(2006)Applying Parallel, Dynamic-Resolution Simulations to Accelerate VLSI Power EstimationProceedings of the 2006 Winter Simulation Conference10.1109/WSC.2006.323148(694-702)Online publication date: Dec-2006
https://doi.org/10.1109/WSC.2006.323148
Coburn JRavi SRaghunathan AJoyner WMartin GKahng A(2005)Power emulationProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065764(700-705)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065764

Index Terms

Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

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Rao DWilsey PNicol DFujimoto R(2006)Applying parallel, dynamic-resolution simulations to accelerate VLSI power estimationProceedings of the 38th conference on Winter simulation10.5555/1218112.1218242(694-702)Online publication date: 3-Dec-2006
https://dl.acm.org/doi/10.5555/1218112.1218242
Rao DWilsey P(2006)Applying Parallel, Dynamic-Resolution Simulations to Accelerate VLSI Power EstimationProceedings of the 2006 Winter Simulation Conference10.1109/WSC.2006.323148(694-702)Online publication date: Dec-2006
https://doi.org/10.1109/WSC.2006.323148
Coburn JRavi SRaghunathan AJoyner WMartin GKahng A(2005)Power emulationProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065764(700-705)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065764

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Efficient circuit partitioning algorithms for parallel logic simulation

Parallel gate-level circuit simulation on shared memory architectures

Parallel waveform-Newton algorithms for circuit simulation