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Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

Authors:

Kevin K. Chang,

Abdullah Giray Yağlıkçı,

Saugata Ghose,

Aditya Agrawal,

Niladrish Chatterjee,

Onur MutluAuthors Info & Claims

SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

Page 52

https://doi.org/10.1145/3078505.3078590

Published: 05 June 2017 Publication History

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Abstract

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by manufacturers.

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Balaji SCharumathi DAhmed MAppu A(2024)The influence of job satisfaction on retention of primary healthcare professionals in Tamil NaduInternational Journal of ADVANCED AND APPLIED SCIENCES10.21833/ijaas.2024.02.02511:2(238-247)Online publication date: Feb-2024
https://doi.org/10.21833/ijaas.2024.02.025
Olgun ABostanci FFrancisco de Oliveira Junior GTugrul YBera RYaglikci AHassan HErgin OMutlu O(2024)Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM ArchitectureACM Transactions on Architecture and Code Optimization10.1145/3673653Online publication date: 14-Jun-2024
https://doi.org/10.1145/3673653
Olgun AHassan HYağlıkçı ATuğrul YOrosa LLuo HPatel MErgin OMutlu O(2023)DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328217242:12(5098-5112)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3282172
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Index Terms

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures
2. Hardware

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Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

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Information & Contributors

Information

Published In

SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

June 2017

84 pages

ISBN:9781450350327

DOI:10.1145/3078505

General Chairs:
Bruce Hajek
University of Illinois
,
Sewoong Oh
University of Illinois
,
Program Chairs:
Augustin Chaintreau
Columbia University
,
Leana Golubchik
University of Southern California
,
Zhi-Li Zhang
University of Minnesota

ACM SIGMETRICS Performance Evaluation Review Volume 45, Issue 1
Performance evaluation review
June 2017
70 pages
ISSN:0163-5999
DOI:10.1145/3143314
Editor:
Nidhi Hegde
Bell Labs, Nokia
Issue’s Table of Contents

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2017

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Abstract

Funding Sources

Nvidia
Samsung
Semiconductor Research Corporation
Google
National Science Foundation
Intel Corporation

Conference

SIGMETRICS '17

Sponsor:

SIGMETRICS

SIGMETRICS '17: ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems

June 5 - 9, 2017

Illinois, Urbana-Champaign, USA

Acceptance Rates

SIGMETRICS '17 Abstracts Paper Acceptance Rate 27 of 76 submissions, 36%;

Overall Acceptance Rate 459 of 2,691 submissions, 17%

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Cited By

View all

Balaji SCharumathi DAhmed MAppu A(2024)The influence of job satisfaction on retention of primary healthcare professionals in Tamil NaduInternational Journal of ADVANCED AND APPLIED SCIENCES10.21833/ijaas.2024.02.02511:2(238-247)Online publication date: Feb-2024
https://doi.org/10.21833/ijaas.2024.02.025
Olgun ABostanci FFrancisco de Oliveira Junior GTugrul YBera RYaglikci AHassan HErgin OMutlu O(2024)Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM ArchitectureACM Transactions on Architecture and Code Optimization10.1145/3673653Online publication date: 14-Jun-2024
https://doi.org/10.1145/3673653
Olgun AHassan HYağlıkçı ATuğrul YOrosa LLuo HPatel MErgin OMutlu O(2023)DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328217242:12(5098-5112)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3282172
Qin YLin CHe WSun YMao ZSeok M(2023)CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data RestorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.323829242:9(3078-3091)Online publication date: Sep-2023
https://doi.org/10.1109/TCAD.2023.3238292
Huch KGonzalez-Guerrero PLyles DMichelogiannakis G(2023)Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine LearningIEEE Transactions on Applied Superconductivity10.1109/TASC.2023.327195133:5(1-14)Online publication date: Aug-2023
https://doi.org/10.1109/TASC.2023.3271951
Shivanandamurthy SVatsavai SThakkar ISalehi S(2023)AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129301(1-8)Online publication date: 5-Apr-2023
https://doi.org/10.1109/ISQED57927.2023.10129301
Rohbani NSoleimani MSarbazi-Azad H(2023)CoolDRAM: An Energy-Efficient and Robust DRAM2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED58423.2023.10244464(1-6)Online publication date: 7-Aug-2023
https://doi.org/10.1109/ISLPED58423.2023.10244464
Wang CFeng DTong WLiu J(2023)CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247700(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247700
Oliveira GGhose SGómez-Luna JBoroumand ASavery ARao SQazi SGrignou GThakur RShiu EMutlu O(2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3317884
Chinnakkonda DTavva VSrinivas M(2023)Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM MemoriesMemories - Materials, Devices, Circuits and Systems10.1016/j.memori.2023.100058(100058)Online publication date: May-2023
https://doi.org/10.1016/j.memori.2023.100058
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