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A CAD framework for generating self-checking multipliers based on residue codes

Published: 01 January 1999 Publication History
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References

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    cover image ACM Conferences
    DATE '99: Proceedings of the conference on Design, automation and test in Europe
    January 1999
    730 pages
    ISBN:1581131216
    DOI:10.1145/307418
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    Published: 01 January 1999

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    Author Tags

    1. fault secure circuits
    2. multipliers
    3. residue arithmetic codes
    4. self-checking circuits

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    • (2015)Low-Cost Duplicate MultiplicationProceedings of the 2015 IEEE 22nd Symposium on Computer Arithmetic10.1109/ARITH.2015.29(2-9)Online publication date: 22-Jun-2015
    • (2014)Design of the coarse-grained reconfigurable architecture DART with on-line error detectionMicroprocessors & Microsystems10.1016/j.micpro.2013.12.00438:2(124-136)Online publication date: 1-Mar-2014
    • (2010)Towards Scalability and Reliability of Autonomic Systems on ChipProceedings of the 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops10.1109/ISORCW.2010.13(73-80)Online publication date: 4-May-2010
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    • (2010)Circuit-Level Soft-Error MitigationSoft Errors in Modern Electronic Systems10.1007/978-1-4419-6993-4_8(203-252)Online publication date: 23-Aug-2010
    • (2008)Cost Reduction and Evaluation of a Temporary Faults-Detecting TechniqueDesign, Automation, and Test in Europe10.1007/978-1-4020-6488-3_31(423-438)Online publication date: 2008
    • (2005)The Proof by 2M-1: A Low-Cost Method to Check Arithmetic ComputationsSecurity and Privacy in the Age of Ubiquitous Computing10.1007/0-387-25660-1_39(589-600)Online publication date: 2005
    • (1999)Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer TechnologiesProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836499Online publication date: 26-Apr-1999

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