research-article

On Characterizing Near-Threshold SRAM Failures in FinFET Technology

Authors:

Shrikanth Ganapathy,

John Kalamatianos,

Keith Kasprak,

Steven RaaschAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 53, Pages 1 - 6

https://doi.org/10.1145/3061639.3062292

Published: 18 June 2017 Publication History

Get Access

Abstract

Adoption of near-threshold voltage (NTV) operation in SRAM-based memories has been limited by reduced robustness resulting from marginal transistor operation that results in bit failures. Using silicon measurements from a large sample of 14nm FinFET test chips, we show that our cells operate at frequencies of up to 1GHz with a minimum 15% voltage guardband, below which the cells begin to fail. We find that when operated at 32.5% below nominal voltage, >95% of the lines experience fewer than 2 failures, which can be corrected with SECDED ECC. Our results indicate that for frequencies of up to 1GHz, NTV can help maximize power savings potential while requiring minimal protection.

References

[1]

G. K. Chen, D. Blaauw, T. Mudge, D. Sylvester, and Nam Sung Kim. 2007. Yield-driven near-threshold SRAM design. In ICCAD.

Digital Library

Google Scholar

[2]

Zeshan Chishti, Alaa R Alameldeen, Chris Wilkerson, Wei Wu, and Shih-Lien Lu. 2009. Improving cache lifetime reliability at ultra-low voltages. In MICRO.

Digital Library

Google Scholar

[3]

Hadi Esmaeilzadeh, Emily Blem, Renee St Amant, Karthikeyan Sankaralingam, and Doug Burger. 2011. Dark silicon and the end of multicore scaling. In ISCA.

Digital Library

Google Scholar

[4]

S. Ganapathy, R. Canal, A. Gonzalez, and A. Rubio. 2013. Effectiveness of hybrid recovery techniques on parametric failures. In ISQED.

Google Scholar

[5]

Samuel Karlin. 2014. A first course in stochastic processes. Academic press.

Google Scholar

[6]

A. Park, V. Narayanan, K. Bowman, F. Atallah, A. Artieri, S. S. Yoon, K. Yuen, and D. Hansquine. 2014. Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. In CICC.

Google Scholar

[7]

Nathaniel Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor Mudge, Dennis Sylvester, and David Blaauw. 2012. Assessing the Performance Limits of Parallelized Near-threshold Computing. In DAC.

Digital Library

Google Scholar

[8]

Nathaniel Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor Mudge, Dennis Sylvester, and David Blaauw. 2016. Near-threshold Computing in FinFET Technologies: Opportunities for Improved Voltage Scalability. In DAC.

Digital Library

Google Scholar

[9]

Daniele Rossi, Nicola Timoncini, Michael Spica, and Cecilia Metra. 2011. Error correcting code analysis for cache memory high reliability and performance. In DATE.

Google Scholar

[10]

Changhwan Shin. 2011. Advanced MOSFET designs and implications for SRAM scaling. Ph.D. Dissertation.

Google Scholar

[11]

Amith Singhee and Rob A Rutenbar. 2010. Extreme statistics in nanoscale memory design. Springer Science & Business Media.

Google Scholar

[12]

Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, and Shih-lien Lu. 2010. Reducing Cache Power with Low-cost, Multi-bit Error-correcting Codes. In ISCA.

Digital Library

Google Scholar

[13]

D. H. Yoon and M. Erez. 2009. Flexible cache error protection using an ECC FIFO. In SC.

Digital Library

Google Scholar

Cited By

View all

Mavropoulos MKeramidas GNikolos D(2024)Improving the Performance Predictability of Faulty Data Caches2024 19th European Dependable Computing Conference (EDCC)10.1109/EDCC61798.2024.00034(123-130)Online publication date: 8-Apr-2024
https://doi.org/10.1109/EDCC61798.2024.00034
Stutz DChandramoorthy NHein MSchiele B(2023)Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN AcceleratorsIEEE Transactions on Pattern Analysis and Machine Intelligence10.1109/TPAMI.2022.318197245:3(3632-3647)Online publication date: 1-Mar-2023
https://doi.org/10.1109/TPAMI.2022.3181972
Afzali-Kusha HPedram M(2023)X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory UnitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.324774370:5(1989-2002)Online publication date: May-2023
https://doi.org/10.1109/TCSI.2023.3247743
Show More Cited By

Index Terms

On Characterizing Near-Threshold SRAM Failures in FinFET Technology
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Static memory
  2. Robustness
    1. Fault tolerance
    2. Hardware reliability
      1. Process, voltage and temperature variations

Recommendations

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

We evaluate full-VDD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes ...
A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology
Abstract
In this paper, a new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed. The cell structure comprises six main body transistors having connections similar to commercial 6T ...
Highlights
- A new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed.
FinFET-based SRAM design
ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article
Research
Refereed limited

Conference

DAC '17

Sponsor:

EDAC
SIGDA

DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
223
Total Downloads

Downloads (Last 12 months)20
Downloads (Last 6 weeks)2

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Mavropoulos MKeramidas GNikolos D(2024)Improving the Performance Predictability of Faulty Data Caches2024 19th European Dependable Computing Conference (EDCC)10.1109/EDCC61798.2024.00034(123-130)Online publication date: 8-Apr-2024
https://doi.org/10.1109/EDCC61798.2024.00034
Stutz DChandramoorthy NHein MSchiele B(2023)Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN AcceleratorsIEEE Transactions on Pattern Analysis and Machine Intelligence10.1109/TPAMI.2022.318197245:3(3632-3647)Online publication date: 1-Mar-2023
https://doi.org/10.1109/TPAMI.2022.3181972
Afzali-Kusha HPedram M(2023)X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory UnitsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.324774370:5(1989-2002)Online publication date: May-2023
https://doi.org/10.1109/TCSI.2023.3247743
Wan ZChandramoorthy NSwaminathan KChen PReddi VRaychowdhury A(2023)BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247999(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247999
Reviriego PJunsangsri PLiu SLombardi F(2022)Error-Tolerant Data Sketches Using Approximate Nanoscale Memories and Voltage ScalingIEEE Transactions on Nanotechnology10.1109/TNANO.2021.313939421(16-22)Online publication date: 2022
https://doi.org/10.1109/TNANO.2021.3139394
Yuksel ISalami BErgin OUnsal OKestelman A(2022)MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312007341:6(1663-1673)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3120073
Ozdenizci OLegenstein R(2022)Improving Robustness Against Stealthy Weight Bit-Flip Attacks by Output Code Matching2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)10.1109/CVPR52688.2022.01303(13378-13387)Online publication date: Jun-2022
https://doi.org/10.1109/CVPR52688.2022.01303
Mavropoulos MKeramidas GNikolos D(2022)Enabling efficient sub-block disabled caches using coarse grain spatial predictionsMicroprocessors and Microsystems10.1016/j.micpro.2022.10447990(104479)Online publication date: Apr-2022
https://doi.org/10.1016/j.micpro.2022.104479
Kadam GSmirni EJog A(2021)Data-centric Reliability Management in GPUs2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN48987.2021.00040(271-283)Online publication date: Jun-2021
https://doi.org/10.1109/DSN48987.2021.00040
Valero ASuarez-Gracia DGran-Tejero R(2020)DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register FilesIEEE Access10.1109/ACCESS.2020.30258998(173276-173288)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3025899
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

FinFET-based SRAM design