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Making DRAM Stronger Against Row Hammering

Published: 18 June 2017 Publication History

Abstract

Modern DRAM suffers from a new problem called row hammering. The problem is expected to become more severe in future DRAMs mostly due to increased inter-row coupling at advanced technology. In order to address this problem, we present a probabilistically managed table (called PRoHIT) implemented on the DRAM chip. The table keeps track of victim row candidates in a probabilistic way and, in case of auto-refresh, the topmost entry is additionally refreshed thereby mitigating the row hammering problem. Our experiments with PARSEC benchmark and synthetic traces show that PRoHIT outperforms the state-of-the-art method, PARA, by 35.7% (PARSEC) in terms of the reduction ratio of row-hammer cases. Our proposed method also shows constantly superior performance to PARA for synthetic traces.

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Cited By

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  • (2024)Rowhammer Attacks in Dynamic Random-Access Memory and Defense MethodsSensors10.3390/s2402059224:2(592)Online publication date: 17-Jan-2024
  • (2024)Mitigation of 1-Row Hammer in BCAT Structures Through Buried Oxide Integration and Investigation of Inter-Cell DisturbancesElectronics10.3390/electronics1324493613:24(4936)Online publication date: 13-Dec-2024
  • (2024)Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)Electronics10.3390/electronics1304068113:4(681)Online publication date: 7-Feb-2024
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cover image ACM Conferences
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017
June 2017
533 pages
ISBN:9781450349277
DOI:10.1145/3061639
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 June 2017

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Author Tags

  1. DRAM
  2. Row hammering
  3. aggressor row
  4. history-based
  5. victim row

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Cited By

View all
  • (2024)Rowhammer Attacks in Dynamic Random-Access Memory and Defense MethodsSensors10.3390/s2402059224:2(592)Online publication date: 17-Jan-2024
  • (2024)Mitigation of 1-Row Hammer in BCAT Structures Through Buried Oxide Integration and Investigation of Inter-Cell DisturbancesElectronics10.3390/electronics1324493613:24(4936)Online publication date: 13-Dec-2024
  • (2024)Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)Electronics10.3390/electronics1304068113:4(681)Online publication date: 7-Feb-2024
  • (2024)Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word LinesApplied Sciences10.3390/app14221034814:22(10348)Online publication date: 11-Nov-2024
  • (2024)SMS: Solving Many-sided RowHammerProceedings of the International Symposium on Memory Systems10.1145/3695794.3695802(78-88)Online publication date: 30-Sep-2024
  • (2024)Cache Line Pinning for Mitigating Row Hammer AttackProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673114(802-811)Online publication date: 12-Aug-2024
  • (2024)Rubix: Reducing the Overhead of Secure Rowhammer Mitigations via Randomized Line-to-Row MappingProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640404(1014-1028)Online publication date: 27-Apr-2024
  • (2024)ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00073(935-948)Online publication date: 2-Nov-2024
  • (2024)BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00072(915-934)Online publication date: 2-Nov-2024
  • (2024)Reducing the Silicon Area Overhead of Counter-Based Rowhammer MitigationsIEEE Computer Architecture Letters10.1109/LCA.2023.332882423:1(61-64)Online publication date: Jan-2024
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