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Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Authors:

Kaicheng Zhang,

Seda Ogrenci-MemikAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 3, Pages 1 - 6

https://doi.org/10.1145/3061639.3062197

Published: 18 June 2017 Publication History

Abstract

We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.

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Cited By

Lin STsai CKao W(2024)Dynamic Precision-Scalable Thermal Mapping Algorithm for Three Dimensional Systolic-Array Based Neural Network AcceleratorIEEE Transactions on Consumer Electronics10.1109/TCE.2024.337870670:1(757-769)Online publication date: 21-Mar-2024
https://dl.acm.org/doi/10.1109/TCE.2024.3378706
Siddhu LBagchi AKedia RAhmad IPandey SPanda P(2023)Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel ClosureACM Transactions on Embedded Computing Systems10.1145/362458122:6(1-27)Online publication date: 9-Nov-2023
https://dl.acm.org/doi/10.1145/3624581
Han JWest RTorres-Castro KSwami NKhan SStan M(2021)Power and Thermal Modeling of In-3D-Memory Computing2021 International Symposium on Devices, Circuits and Systems (ISDCS)10.1109/ISDCS52006.2021.9397913(1-4)Online publication date: 3-Mar-2021
https://doi.org/10.1109/ISDCS52006.2021.9397913
Show More Cited By

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

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DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Lin STsai CKao W(2024)Dynamic Precision-Scalable Thermal Mapping Algorithm for Three Dimensional Systolic-Array Based Neural Network AcceleratorIEEE Transactions on Consumer Electronics10.1109/TCE.2024.337870670:1(757-769)Online publication date: 21-Mar-2024
https://dl.acm.org/doi/10.1109/TCE.2024.3378706
Siddhu LBagchi AKedia RAhmad IPandey SPanda P(2023)Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel ClosureACM Transactions on Embedded Computing Systems10.1145/362458122:6(1-27)Online publication date: 9-Nov-2023
https://dl.acm.org/doi/10.1145/3624581
Han JWest RTorres-Castro KSwami NKhan SStan M(2021)Power and Thermal Modeling of In-3D-Memory Computing2021 International Symposium on Devices, Circuits and Systems (ISDCS)10.1109/ISDCS52006.2021.9397913(1-4)Online publication date: 3-Mar-2021
https://doi.org/10.1109/ISDCS52006.2021.9397913
Han JTorres-Castro KWest RSwami NStan M(2021)Thermal Analysis of Microfluidic cooling in Processing-in-3D-Stacked Memory2021 22nd International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)10.1109/EuroSimE52062.2021.9410836(1-6)Online publication date: 19-Apr-2021
https://doi.org/10.1109/EuroSimE52062.2021.9410836
Zhou MProdromou AWang RYang HQian DTullsen D(2020)Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292752839:10(1973-1986)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2927528
Yoon CShim JMoon BKong J(2018)3D die-stacked DRAM thermal management via task allocation and core pipeline controlIEICE Electronics Express10.1587/elex.15.2017125315:3(20171253-20171253)Online publication date: 2018
https://doi.org/10.1587/elex.15.20171253

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