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Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM

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Qiang DouAuthors Info & Claims

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

Pages 281 - 286

https://doi.org/10.1145/3060403.3060423

Published: 10 May 2017 Publication History

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Abstract

In embedded processors, the RAM resources required by branch predictor compared to desktop or server processors are far from being reached. Utilizing the limited resources to design superior performance branch predictor has become urgent challenge. In this paper, we exploit the performance of complex TAGE implemented in ultra-small RAM processor. We first define design space exploration problem of the TAGE under the constraints of given RAM size and maximum global history register length. Then, based on the trace-driven simulation, the improved Particle Swarm Optimization algorithm is used to efficiently explore the specific parameters, rewarding design parameters with high prediction accuracy under RAM ranging from 0.125KB to 4KB. We found that, for the traces of this paper, the parameters under the 1.5KB RAM explored by our algorithm can achieve adequate accuracy. The performance loss is considerably small if we reduce the RAM resources from 8KB to 1.5KB. In addition, the misprediction rate of 1.5KB TAGE are reduced by 63.41% compared to 1.5KB Bi-mode. And, 0.25KB TAGE has almost the same accuracy with 4KB GShare.

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Cited By

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Li MXu RZhang HLi LLi Y(2024)CMA-BP: A Clustered Multi-Task Learning and Branch Attention Based Branch Predictor2024 IEEE International Conference on Systems, Man, and Cybernetics (SMC)10.1109/SMC54092.2024.10831163(1370-1376)Online publication date: 6-Oct-2024
https://doi.org/10.1109/SMC54092.2024.10831163
Vougioukas INikoleris NSandberg ADiestelhorst SAl-Hashimi BMerrett G(2019)BRB: Mitigating Branch Predictor Side-Channels2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00058(466-477)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00058
Ma JYu QHuang LGuo HQian CMa SWang Z(2018)Improving Branch Prediction Accuracy on Multi-Core Architectures for Big Data2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)10.1109/BDCloud.2018.00065(377-382)Online publication date: Dec-2018
https://doi.org/10.1109/BDCloud.2018.00065
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Index Terms

Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM
1. Hardware
  1. Very large scale integration design

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Published In

GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

May 2017

516 pages

ISBN:9781450349727

DOI:10.1145/3060403

General Chairs:
Laleh Behjat
University of Calgary, Canada
,
Jie Han
University of Alberta, Canada
,
Program Chairs:
Miroslav N. Velev
Aries Design Automation, USA
,
Deming Chen
University of Illinois, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 May 2017

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GLSVLSI '17: Great Lakes Symposium on VLSI 2017

May 10 - 12, 2017

Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Li MXu RZhang HLi LLi Y(2024)CMA-BP: A Clustered Multi-Task Learning and Branch Attention Based Branch Predictor2024 IEEE International Conference on Systems, Man, and Cybernetics (SMC)10.1109/SMC54092.2024.10831163(1370-1376)Online publication date: 6-Oct-2024
https://doi.org/10.1109/SMC54092.2024.10831163
Vougioukas INikoleris NSandberg ADiestelhorst SAl-Hashimi BMerrett G(2019)BRB: Mitigating Branch Predictor Side-Channels2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00058(466-477)Online publication date: Feb-2019
https://doi.org/10.1109/HPCA.2019.00058
Ma JYu QHuang LGuo HQian CMa SWang Z(2018)Improving Branch Prediction Accuracy on Multi-Core Architectures for Big Data2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)10.1109/BDCloud.2018.00065(377-382)Online publication date: Dec-2018
https://doi.org/10.1109/BDCloud.2018.00065
Zhou CHuang LZhang TWang YZhang CDou Q(2017)Effective Optimization of Branch Predictors through Lightweight Simulation2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.114(653-656)Online publication date: Nov-2017
https://doi.org/10.1109/ICCD.2017.114
Zhang TZhou CHuang LXiao NMa S(2017)Improving Branch Prediction for Thread Migration on Multi-core ArchitecturesNetwork and Parallel Computing10.1007/978-3-319-68210-5_8(87-99)Online publication date: 20-Oct-2017
https://dl.acm.org/doi/10.1007/978-3-319-68210-5_8

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Recommendations

An Alternative TAGE-like Conditional Branch Predictor

A new case for the TAGE branch predictor

Efficient architectural exploration of TAGE branch predictor for embedded processors

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