Under-the-Cell Routing to Improve Manufacturability
Pages 125 - 130
Abstract
The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed in a way that they can be treated as black boxes during physical design. However, this abstraction often prevents an efficient use of its internal free resources.
>This paper proposes an effective approach for using internal routing resources without sacrificing modularity. By using cell generation tools for regular layouts, libraries are enriched with cell instances that have lateral pins and allow under-the-cell connections between adjacent cells, thus reducing pin count, via count and routing congestion.
An approach to generate cells with regular layouts and lateral pins is proposed. Additionally, algorithms to maximize the impact of under-the-cell routing are presented. The proposed techniques are integrated in an industrial design flow. Experimental results show a significant reduction of design rule check violations with negligible impact on timing.
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D. Pan, B. Yu, and J.-R. Gao. Design for Manufacturing With Emerging Nanolithography. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(10):1453--1472, Oct. 2013.
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P. Saxena, R. S. Shelar, and S. S. Sapatnekar. Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on Integrated Circuits and Systems. Springer, 2007.
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Index Terms
- Under-the-Cell Routing to Improve Manufacturability
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Information
Published In
May 2017
516 pages
ISBN:9781450349727
DOI:10.1145/3060403
- General Chairs:
- Laleh Behjat,
- Jie Han,
- Program Chairs:
- Miroslav N. Velev,
- Deming Chen
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Published: 10 May 2017
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- Agència de Gestió d'Ajuts Universitaris i de Recerca
- European Regional Development Fund
- Ministerio de Economía y Competitividad
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Overall Acceptance Rate 312 of 1,156 submissions, 27%
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