Article

Free access

A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation3

Authors:

Thomas Sterling,

Larry BergmanAuthors Info & Claims

ICS '99: Proceedings of the 13th international conference on Supercomputing

Pages 286 - 293

https://doi.org/10.1145/305138.305205

Published: 01 May 1999 Publication History

PDF eReader

References

[1]

D. Psaltis and F. Mok, "Holographic Memories," Scientific American, Nov 1995, Vol. 273, No. 5, pp. 70-76.

Google Scholar

[2]

I. Redmond, R. Linke, E. Chuang, and D. Psaltis, "Holographic Data Storage in a DX-Center Material," Optics Letters 22:(15), pp. 1189-1191, Aug 1, 1997.

Google Scholar

[3]

P. Kogge, S. Bass, J. Brockman, D. Chen, and E. Sha, "Pursuing a Petaflop: Point Designs for 100TF Computers Using PIM Technologies," Frontiers of Massively Parallel Computation, Oct 1996.

Digital Library

Google Scholar

[4]

J. Cohen, "Mix of Technologies Spurs Future Supercomputer," NASA Insights, July 1998, pp. 2-11.

Google Scholar

[5]

T. Sterling, "In Pursuit of a Quadrillion Operations per Second," NASA Insights, April 1998, pp. 8-11.

Google Scholar

[6]

M. Dorojevets, P. Bunyk, D. Zinoviev, and K. Likharev, "Petaflops RSFQ System Design, "IEEE Transaction Applied Superconductivity, in press.

Google Scholar

[7]

K. Likharev, "Ultrafast Superconductor Digital Electronics: RSFQ Technology Roadmap," Czeehoslovok J. Physics, vol. 46, Supplement S6, 1996.

Google Scholar

[8]

T. Sterling, P. Messina, and P.H. Smith, Enabling Technologies for Peta(FL)OPS Computing, MIT Press, Cambridge, MA, 1995.

Digital Library

Google Scholar

[9]

K. Likharev, "Superconductors Speed Up Computation," Physics World, May 1997, pp. 39-43.

Google Scholar

[10]

K. Likharev, "RSFQ Digital Electronics: Achievements, Prospects, and Problems (Invited)," Appl. Superconductivity Conf., Palm Desert, CA, Sept 13-18, 1998.

Google Scholar

[11]

L. Abelson, Q. Herr, G. Kerber, M. Leung, and T. Tighe, "Full Scale Integration of Superconductor Electronics for Petafiops Computing "2nd Conf. for Enabling Technologies for Petaflops Computing, Santa Barbara, Feb 1999.

Google Scholar

[12]

K. Bergman, "Ultra-High Speed Optical LANs," Conference on Optical Fiber Communications (0FC'98), Workshop on LANs and WANs, San Jose, CA, Feb 1998.

Google Scholar

[13]

B. Smith, "Alternatives and Imperatives for Optical Interconnects in High Performance Computers," OSA Spring Topical Meeting on Optical Computing, Lake Tahoe, CA, Session JTuC I, March 18, 1997.

Google Scholar

[14]

K. Gaj, Q. Herr, V. Adler, A. Krasnicwski, E. Friedman, and M. Feldman, "Tools for the Computer-Aided Design of Multi-Gigahertz Superconducting Digital Circuits," HTMT TechNote, No. 26, submitted for ext. publication, Oct 1998.

Google Scholar

[15]

K. Gaj, E. Friedman, and M. Feldman, "Timing of Multi- Gigahertz Rapid Single Flux Quantum Digital Circuits," Journal of VLSI Signal Processing, Kluwer Academic Publishers, The Netherlands, No. 16, pp. 247-276 (1997).

Digital Library

Google Scholar

[16]

P. Kogge, J. Broekman, T. Sterling, and G. Gao, "Processing in Memory: Chips to Petafiops," ICSA Workshop on Mixing Logic and DRAM, June 1, 1997.

Google Scholar

[17]

G. Gao, K. Theobald, A. Marquez, and T. Sterling, "The HTMT Program Execution Model," University of Delaware, Department of Electrical and Computer Engineering, CAPSL Technical Memo No. 9, July 18, 1997.

Google Scholar

Cited By

View all

Filippov TDorojevets MSahu AKirichenko AAyala CMukhanov O(2011)8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic UnitIEEE Transactions on Applied Superconductivity10.1109/TASC.2010.210391821:3(847-851)Online publication date: Jun-2011
https://doi.org/10.1109/TASC.2010.2103918
Qian DZhu D(2009)Challenges and possible approaches: towards the petaflops computersFrontiers of Computer Science in China10.1007/s11704-009-0022-63:3(273-289)Online publication date: 29-Jul-2009
https://doi.org/10.1007/s11704-009-0022-6
Brockman JThoziyoor SKuntz SKogge PCarter JZhang L(2004)A low cost, multithreaded processing-in-memory systemProceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture10.1145/1054943.1054946(16-22)Online publication date: 20-Jun-2004
https://dl.acm.org/doi/10.1145/1054943.1054946
Show More Cited By

Index Terms

Recommendations

Power-Sensitive Multithreaded Architecture
ICCD '00: Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, ...
An analysis of operating system behavior on a simultaneous multithreaded architecture
ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, ...
An analysis of operating system behavior on a simultaneous multithreaded architecture
Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICS '99: Proceedings of the 13th international conference on Supercomputing

June 1999

509 pages

ISBN:158113164X

DOI:10.1145/305138

Chairmen:
Theodore Papatheodorou
Univ. of Patras, Patras, Greece
,
Mateo Valero
Univ. Politècnica de Catalunya, Barcelona, Spain
,
Constantine D. Polychronopoulos
Univ. of Illinois
,
Yoichi Muraoka
Waseda Univ.
,
Jesus Labarta
Univ. Politècnica de Catalunya, Barcelona, Spain

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1999

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICS99

Sponsor:

SIGARCH

ICS99: The 13th ACM International Conference on Supercomputing

June 20 - 25, 1999

Rhodes, Greece

Acceptance Rates

ICS '99 Paper Acceptance Rate 57 of 180 submissions, 32%;

Overall Acceptance Rate 629 of 2,180 submissions, 29%

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
650
Total Downloads

Downloads (Last 12 months)66
Downloads (Last 6 weeks)7

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Filippov TDorojevets MSahu AKirichenko AAyala CMukhanov O(2011)8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic UnitIEEE Transactions on Applied Superconductivity10.1109/TASC.2010.210391821:3(847-851)Online publication date: Jun-2011
https://doi.org/10.1109/TASC.2010.2103918
Qian DZhu D(2009)Challenges and possible approaches: towards the petaflops computersFrontiers of Computer Science in China10.1007/s11704-009-0022-63:3(273-289)Online publication date: 29-Jul-2009
https://doi.org/10.1007/s11704-009-0022-6
Brockman JThoziyoor SKuntz SKogge PCarter JZhang L(2004)A low cost, multithreaded processing-in-memory systemProceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture10.1145/1054943.1054946(16-22)Online publication date: 20-Jun-2004
https://dl.acm.org/doi/10.1145/1054943.1054946
Rodrigues AMurphy RKogge PUnderwood KFeautrier PGoodman JSeznec A(2004)Characterizing a new class of threads in scientific applications for high end supercomputersProceedings of the 18th annual international conference on Supercomputing10.1145/1006209.1006234(164-174)Online publication date: 26-Jun-2004
https://dl.acm.org/doi/10.1145/1006209.1006234
Upchurch ESterling TBrockman JHuskamp J(2004)Analysis and Modeling of Advanced PIM Architecture Design TradeoffsProceedings of the 2004 ACM/IEEE conference on Supercomputing10.1109/SC.2004.11Online publication date: 6-Nov-2004
https://dl.acm.org/doi/10.1109/SC.2004.11
Sterling TZima HGiles RReed DKelley K(2002)GilgameshProceedings of the 2002 ACM/IEEE conference on Supercomputing10.5555/762761.762763(1-23)Online publication date: 16-Nov-2002
https://dl.acm.org/doi/10.5555/762761.762763
Murphy RKogge P(2002)Trading bandwidth for latency: managing continuations through a carpet bag cacheInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems10.1109/IWIA.2002.1035017(41-49)Online publication date: 2002
https://doi.org/10.1109/IWIA.2002.1035017
Almasi GCaşcaval CCastaños JDenneau MDonath WEleftheriou MGiampapa MHo HLieber DMoreira JNewns DSnir MWarren H(2002)Demonstrating the Scalability of a Molecular Dynamics Application on a Petaflops ComputerInternational Journal of Parallel Programming10.1023/A:101985602991830:4(317-351)Online publication date: 1-Aug-2002
https://dl.acm.org/doi/10.1023/A%3A1019856029918
Xiaogang Qiu Dubois M(2001)Towards virtually-addressed memory hierarchiesProceedings HPCA Seventh International Symposium on High-Performance Computer Architecture10.1109/HPCA.2001.903251(51-62)Online publication date: 2001
https://doi.org/10.1109/HPCA.2001.903251
Murphy RKogge PRodrigues A(2001)The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆Intelligent Memory Systems10.1007/3-540-44570-6_6(85-103)Online publication date: 5-Sep-2001
https://doi.org/10.1007/3-540-44570-6_6
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Power-Sensitive Multithreaded Architecture

An analysis of operating system behavior on a simultaneous multithreaded architecture

An analysis of operating system behavior on a simultaneous multithreaded architecture