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A non von neumann continuum computer architecture for scalability beyond Moore's law

Published: 16 May 2016 Publication History

Abstract

A strategic challenge confronting the continued advance of high performance computing (HPC) to extreme scale is the approaching near-nanoscale semiconductor technology and the end of Moore's Law. This paper introduces the foundations of an innovative class of parallel architecture reversing many of the conventional architecture directions, but benefiting from substantial prior art of previous decades. The Continuum Computer Architecture, or CCA, eschews traditional von Neumann-derived processing logic, instead employing structures composed of fine-grain cells (fontons) that combine functional units, memory, and network. The paper describes how CCA systems of various scales may be organized and implemented using currently available technology. As programming of such systems substantially differs from established practices, a still experimental ParalleX execution model is introduced to be used as a guide for the implementation of related software stack layers, ranging from the operating system to application level constructs. Finally, the HPX-5 runtime system, an advanced implementation of ParalleX core components, is presented as an intermediate software methodology for CCA system computation resource management.

References

[1]
HPX-5 web page. http://hpx.crest.iu.edu/.
[2]
H. C. Baker and C. Hewitt. The incremental garbage collection of processes. In SIGART Bull., pages 55--59, New York, NY, USA, August 1977. ACM.
[3]
C. Dekate et al. Improving the scalability of parallel N-body applications with an event driven constraint based execution model. The International Journal of High Performance Computing Applications, 2012.
[4]
H. Kaiser, M. Brodowicz, and T. Sterling. ParalleX: An Advanced Parallel Execution Model for Scaling-Impaired Applications. In Parallel Processing Workshops, pages 394--401. IEEE Computer Society, 2009.
[5]
T. Sterling, D. Kogler, M. Anderson, and M. Brodowicz. SLOWER: A performance model for exascale computing. Supercomputing Frontiers and Innovations, 1(2), 2014.
[6]
S. Yang, M. Brodowicz, H. Kaiser, and W. Ligon. PXFS: A persistent storage model for extreme scale. In Proceedings of the Workshop on Computing, Networking, and Communications, ICNC'14, 2014.

Cited By

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  • (2017)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource SharingInternational Journal of Networking and Computing10.15803/ijnc.7.2_1547:2(154-172)Online publication date: 2017
  • (2016)FPGA-based Annealing Processor for Ising Model2016 Fourth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR.2016.0081(436-442)Online publication date: Nov-2016

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Information

Published In

cover image ACM Conferences
CF '16: Proceedings of the ACM International Conference on Computing Frontiers
May 2016
487 pages
ISBN:9781450341288
DOI:10.1145/2903150
  • General Chairs:
  • Gianluca Palermo,
  • John Feo,
  • Program Chairs:
  • Antonino Tumeo,
  • Hubertus Franke
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 May 2016

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Author Tags

  1. computer architecture
  2. extreme scale
  3. parallel computing

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CF'16
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CF'16: Computing Frontiers Conference
May 16 - 19, 2016
Como, Italy

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CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;
Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

View all
  • (2017)Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource SharingInternational Journal of Networking and Computing10.15803/ijnc.7.2_1547:2(154-172)Online publication date: 2017
  • (2016)FPGA-based Annealing Processor for Ising Model2016 Fourth International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR.2016.0081(436-442)Online publication date: Nov-2016

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