poster

An architecture for near-data processing systems

Authors:

Erik Vermij,

Christoph Hagleitner,

Leandro Fiorin,

Rik Jongerius,

Jan van Lunteren,

Koen BertelsAuthors Info & Claims

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

Pages 357 - 360

https://doi.org/10.1145/2903150.2903478

Published: 16 May 2016 Publication History

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Abstract

Near-data processing is a promising paradigm to address the bandwidth, latency, and energy limitations in today's computer systems. In this work, we introduce an architecture that enhances a contemporary multi-core CPU with new features for supporting a seamless integration of near-data processing capabilities. Crucial aspects such as coherency, data placement, communication, address translation, and the programming model are discussed. The essential components, as well as a system simulator, are realized in hardware and software. Results for the important Graph500 benchmark show a 1.5x speedup when using the proposed architecture.

References

[1]

J. Ahn and et al. PIM-enabled Instructions: A Low-overhead, Locality-aware Processing-in-memory Architecture. In Annual International Symposium on Computer Architecture, (ISCA), pages 336--348, New York, NY, USA, 2015. ACM.

Digital Library

Google Scholar

[2]

E. Azarkhish and et al. High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (DATE), pages 1317--1322, San Jose, CA, USA, 2015. EDA Consortium.

Digital Library

Google Scholar

[3]

R. Balasubramonian and et al. Near-Data Processing: Insights from a MICRO-46 Workshop. Micro, IEEE, 34(4):36--42, July 2014.

Crossref

Google Scholar

[4]

M. Chu and et al. High-level Programming Model Abstractions for Processing in Memory. In 1st Workshop on Near-Data Processing in conjunction with the International Symposium on Microarchitecture, (WoNDP), 2013.

Google Scholar

[5]

A. De and et al. Minerva: Accelerating Data Analysis in Next-Generation SSDs. In IEEE International Symposium on Field-Programmable Custom Computing Machines, (FCCM), Seattle, WA, USA, pages 9--16, 2013.

Digital Library

Google Scholar

[6]

A. Farmahini-Farahani and et al. NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. In High Performance Computer Architecture, 2015, (HPCA), pages 283--295, Feb 2015.

Google Scholar

[7]

Z. Guz and et al. Real-Time Analytics as the Killer Application for Processing-In-Memory. 2nd Workshop on Near-Data Processing (WoNDP), 2014.

Google Scholar

[8]

R. Nair and et al. Active Memory Cube: A processing-in-memory architecture for exascale systems. IBM Journal of Research and Development, 59(2/3):17:1--17:14, March 2015.

Digital Library

Google Scholar

[9]

E. Panainte, K. Bertels, and S. Vassiliadis. Compiling for the Molen Programming Paradigm. In P. Y. K. Cheung and G. Constantinides, editors, Field Programmable Logic and Application, volume 2778 of Lecture Notes in Computer Science, pages 900--910. Springer Berlin Heidelberg, 2003.

Crossref

Google Scholar

[10]

S. Pugsley and et al. Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. Micro, IEEE, 34(4):44--52, July 2014.

Crossref

Google Scholar

[11]

W. Starke and et al. The cache and memory subsystems of the IBM POWER8 processor. IBM Journal of Research and Development, 59(1):3:1--3:13, Jan 2015.

Digital Library

Google Scholar

[12]

P. Trancoso. Moving to Memoryland: In-memory Computation for Existing Applications. In ACM International Conference on Computing Frontiers, (CF), pages 32:1--32:6, New York, NY, USA, 2015. ACM.

Digital Library

Google Scholar

Cited By

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Fife RUdoh IGarcia P(2020)Coherency overhead of Processing-in-Memory in the presence of shared data2020 IEEE International Conference on Industrial Technology (ICIT)10.1109/ICIT45562.2020.9067234(237-242)Online publication date: Feb-2020
https://doi.org/10.1109/ICIT45562.2020.9067234
Ozdal M(2018)Emerging Accelerator Platforms for Data CentersIEEE Design & Test10.1109/MDAT.2017.277974235:1(47-54)Online publication date: Feb-2018
https://doi.org/10.1109/MDAT.2017.2779742
Vermij EFiorin LHagleitner CBertels K(2017)Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing2017 46th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2017.12(31-40)Online publication date: Aug-2017
https://doi.org/10.1109/ICPP.2017.12

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Information & Contributors

Information

Published In

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

May 2016

487 pages

ISBN:9781450341288

DOI:10.1145/2903150

General Chairs:
Gianluca Palermo
Politecnico di Milano, IT
,
John Feo
Pacific Northwest National Laboratory and Northwest Institute for Advanced Computing
,
Program Chairs:
Antonino Tumeo
Pacific Northwest National Laboratory, USA
,
Hubertus Franke
New York University and IBM Research, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 May 2016

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Qualifiers

Poster

Funding Sources

ASTRON, The Netherlands

Conference

CF'16

Sponsor:

Micron Foundation
ACM
Politecnico di Milano
SIGMICRO
IBM

CF'16: Computing Frontiers Conference

May 16 - 19, 2016

Como, Italy

Acceptance Rates

CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;

Overall Acceptance Rate 273 of 785 submissions, 35%

Upcoming Conference

CF '25

Sponsor:
sigmicro

22nd ACM International Conference on Computing Frontiers

May 28 - 30, 2025

Cagliari , Italy

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Cited By

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Fife RUdoh IGarcia P(2020)Coherency overhead of Processing-in-Memory in the presence of shared data2020 IEEE International Conference on Industrial Technology (ICIT)10.1109/ICIT45562.2020.9067234(237-242)Online publication date: Feb-2020
https://doi.org/10.1109/ICIT45562.2020.9067234
Ozdal M(2018)Emerging Accelerator Platforms for Data CentersIEEE Design & Test10.1109/MDAT.2017.277974235:1(47-54)Online publication date: Feb-2018
https://doi.org/10.1109/MDAT.2017.2779742
Vermij EFiorin LHagleitner CBertels K(2017)Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing2017 46th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2017.12(31-40)Online publication date: Aug-2017
https://doi.org/10.1109/ICPP.2017.12

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Toward standardized near-data processing with unrestricted data placement for GPUs